iommu/arm-smmu: Workaround for ThunderX erratum #27704 (1bd37a68) · Commits · e / devices / android_kernel_xiaomi_nabu

Documentation/arm64/silicon-errata.txt

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -57,3 +57,4 @@ stable kernels.
	\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|		\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|
	\| Cavium \| ThunderX GICv3 \| #23154 \| CAVIUM_ERRATUM_23154 \|		\| Cavium \| ThunderX GICv3 \| #23154 \| CAVIUM_ERRATUM_23154 \|
	\| Cavium \| ThunderX Core \| #27456 \| CAVIUM_ERRATUM_27456 \|		\| Cavium \| ThunderX Core \| #27456 \| CAVIUM_ERRATUM_27456 \|
			\| Cavium \| ThunderX SMMUv2 \| #27704 \| N/A \|

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -16,6 +16,7 @@ conditions.
	"arm,mmu-400"		"arm,mmu-400"
	"arm,mmu-401"		"arm,mmu-401"
	"arm,mmu-500"		"arm,mmu-500"
			"cavium,smmu-v2"

	depending on the particular implementation and/or the		depending on the particular implementation and/or the
	version of the architecture implemented.		version of the architecture implemented.

drivers/iommu/arm-smmu.c

+28 −11

Original line number	Original line	Diff line number	Diff line
	@@ -334,6 +334,8 @@ struct arm_smmu_device {

	struct list_head list;		struct list_head list;
	struct rb_root masters;		struct rb_root masters;

			u32 cavium_id_base; /* Specific to Cavium */
	};		};

	struct arm_smmu_cfg {		struct arm_smmu_cfg {
	@@ -343,8 +345,8 @@ struct arm_smmu_cfg {
	};		};
	#define INVALID_IRPTNDX 0xff		#define INVALID_IRPTNDX 0xff

	#define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)		#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
	#define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)		#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)

	enum arm_smmu_domain_stage {		enum arm_smmu_domain_stage {
	ARM_SMMU_DOMAIN_S1 = 0,		ARM_SMMU_DOMAIN_S1 = 0,
	@@ -372,6 +374,8 @@ struct arm_smmu_option_prop {
	const char *prop;		const char *prop;
	};		};

			static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);

	static struct arm_smmu_option_prop arm_smmu_options[] = {		static struct arm_smmu_option_prop arm_smmu_options[] = {
	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },		{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
	{ 0, NULL},		{ 0, NULL},
	@@ -583,11 +587,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)

	if (stage1) {		if (stage1) {
	base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
	writel_relaxed(ARM_SMMU_CB_ASID(cfg),		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
	base + ARM_SMMU_CB_S1_TLBIASID);		base + ARM_SMMU_CB_S1_TLBIASID);
	} else {		} else {
	base = ARM_SMMU_GR0(smmu);		base = ARM_SMMU_GR0(smmu);
	writel_relaxed(ARM_SMMU_CB_VMID(cfg),		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
	base + ARM_SMMU_GR0_TLBIVMID);		base + ARM_SMMU_GR0_TLBIVMID);
	}		}

	@@ -609,7 +613,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,

	if (!IS_ENABLED(CONFIG_64BIT) \|\| smmu->version == ARM_SMMU_V1) {		if (!IS_ENABLED(CONFIG_64BIT) \|\| smmu->version == ARM_SMMU_V1) {
	iova &= ~12UL;		iova &= ~12UL;
	iova \|= ARM_SMMU_CB_ASID(cfg);		iova \|= ARM_SMMU_CB_ASID(smmu, cfg);
	do {		do {
	writel_relaxed(iova, reg);		writel_relaxed(iova, reg);
	iova += granule;		iova += granule;
	@@ -617,7 +621,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
	#ifdef CONFIG_64BIT		#ifdef CONFIG_64BIT
	} else {		} else {
	iova >>= 12;		iova >>= 12;
	iova \|= (u64)ARM_SMMU_CB_ASID(cfg) << 48;		iova \|= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
	do {		do {
	writeq_relaxed(iova, reg);		writeq_relaxed(iova, reg);
	iova += granule >> 12;		iova += granule >> 12;
	@@ -637,7 +641,7 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
	#endif		#endif
	} else {		} else {
	reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
	writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg);		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
	}		}
	}		}

	@@ -746,7 +750,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
	#endif		#endif
	/* 16-bit VMIDs live in CBA2R */		/* 16-bit VMIDs live in CBA2R */
	if (smmu->features & ARM_SMMU_FEAT_VMID16)		if (smmu->features & ARM_SMMU_FEAT_VMID16)
	reg \|= ARM_SMMU_CB_VMID(cfg) << CBA2R_VMID_SHIFT;		reg \|= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;

	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
	}		}
	@@ -765,7 +769,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
	(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);		(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {		} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
	/* 8-bit VMIDs live in CBAR */		/* 8-bit VMIDs live in CBAR */
	reg \|= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT;		reg \|= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
	}		}
	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));

	@@ -773,11 +777,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
	if (stage1) {		if (stage1) {
	reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

	reg64 \|= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;		reg64 \|= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
	smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR0);

	reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
	reg64 \|= ((u64)ARM_SMMU_CB_ASID(cfg)) << TTBRn_ASID_SHIFT;		reg64 \|= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
	smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);		smmu_writeq(reg64, cb_base + ARM_SMMU_CB_TTBR1);
	} else {		} else {
	reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
	@@ -1737,6 +1741,7 @@ static const struct of_device_id arm_smmu_of_match[] = {
	{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },		{ .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 },
	{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },		{ .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 },
	{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },		{ .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 },
			{ .compatible = "cavium,smmu-v2", .data = (void *)ARM_SMMU_V2 },
	{ },		{ },
	};		};
	MODULE_DEVICE_TABLE(of, arm_smmu_of_match);		MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
	@@ -1847,6 +1852,18 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
	}		}
	}		}

			/*
			* Cavium CN88xx erratum #27704.
			* Ensure ASID and VMID allocation is unique across all SMMUs in
			* the system.
			*/
			if (of_device_is_compatible(dev->of_node, "cavium,smmu-v2")) {
			smmu->cavium_id_base =
			atomic_add_return(smmu->num_context_banks,
			&cavium_smmu_context_count);
			smmu->cavium_id_base -= smmu->num_context_banks;
			}

	INIT_LIST_HEAD(&smmu->list);		INIT_LIST_HEAD(&smmu->list);
	spin_lock(&arm_smmu_devices_lock);		spin_lock(&arm_smmu_devices_lock);
	list_add(&smmu->list, &arm_smmu_devices);		list_add(&smmu->list, &arm_smmu_devices);

Original line number	Original line	Diff line number	Diff line
	@@ -57,3 +57,4 @@ stable kernels.
	\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|		\| Cavium \| ThunderX ITS \| #22375, #24313 \| CAVIUM_ERRATUM_22375 \|
	\| Cavium \| ThunderX GICv3 \| #23154 \| CAVIUM_ERRATUM_23154 \|		\| Cavium \| ThunderX GICv3 \| #23154 \| CAVIUM_ERRATUM_23154 \|
	\| Cavium \| ThunderX Core \| #27456 \| CAVIUM_ERRATUM_27456 \|		\| Cavium \| ThunderX Core \| #27456 \| CAVIUM_ERRATUM_27456 \|
			\| Cavium \| ThunderX SMMUv2 \| #27704 \| N/A \|