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Commit 1b0e6f8f authored by Vaibhav Deshu Venkatesh's avatar Vaibhav Deshu Venkatesh Committed by Gerrit - the friendly Code Review server
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msm: vidc: Register changes to boot venus 



Change the addresses/offsets of venus registers based on
hardware changes.

CRs-Fixed: 2358497
Change-Id: I2f663fe31b9d95dbd69b56eed955c631daec163d
Signed-off-by: default avatarVaibhav Deshu Venkatesh <vdeshuve@codeaurora.org>
parent 3fa9bf87

drivers/media/platform/msm/vidc/venus_hfi.c

+3 −3
Original line number Diff line number Diff line
@@ -1497,7 +1497,7 @@ static int __iface_cmdq_write(struct venus_hfi_device *device, void *pkt) 
		/* Consumer of cmdq prefers that we raise an interrupt */

		rc = 0;

		__write_register(device, VIDC_CPU_IC_SOFTINT,

				1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

	}



	return rc;
@@ -1533,7 +1533,7 @@ static int __iface_msgq_read(struct venus_hfi_device *device, void *pkt) 
		__hal_sim_modify_msg_packet((u8 *)pkt, device);

		if (tx_req_is_set)

			__write_register(device, VIDC_CPU_IC_SOFTINT,

				1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

		rc = 0;

	} else

		rc = -ENODATA;
@@ -1565,7 +1565,7 @@ static int __iface_dbgq_read(struct venus_hfi_device *device, void *pkt) 
	if (!__read_queue(q_info, (u8 *)pkt, &tx_req_is_set)) {

		if (tx_req_is_set)

			__write_register(device, VIDC_CPU_IC_SOFTINT,

				1 << VIDC_CPU_IC_SOFTINT_H2A_SHFT);

				VIDC_CPU_IC_SOFTINT_H2A_SHFT);

		rc = 0;

	} else

		rc = -ENODATA;

drivers/media/platform/msm/vidc/vidc_hfi_io.h

+6 −6
Original line number Diff line number Diff line
@@ -10,11 +10,11 @@ 


#define VIDC_VBIF_BASE_OFFS			0x00080000



#define VIDC_CPU_BASE_OFFS			0x000C0000

#define VIDC_CPU_BASE_OFFS			0x000A0000

#define VIDEO_GCC_BASE_OFFS			0x00000000

#define VIDEO_CC_BASE_OFFS			0x00100000

#define VIDC_CPU_CS_BASE_OFFS		(VIDC_CPU_BASE_OFFS + 0x00012000)

#define VIDC_CPU_IC_BASE_OFFS		(VIDC_CPU_BASE_OFFS + 0x0001F000)

#define VIDC_CPU_CS_BASE_OFFS		(VIDC_CPU_BASE_OFFS)

#define VIDC_CPU_IC_BASE_OFFS		(VIDC_CPU_BASE_OFFS)



#define VIDC_CPU_CS_REMAP_OFFS		(VIDC_CPU_CS_BASE_OFFS + 0x00)

#define VIDC_CPU_CS_TIMER_CONTROL	(VIDC_CPU_CS_BASE_OFFS + 0x04)
@@ -69,9 +69,9 @@ 
#define VIDC_CPU_IC_INTSELECT		(VIDC_CPU_IC_BASE_OFFS + 0x0C)

#define VIDC_CPU_IC_INTENABLE		(VIDC_CPU_IC_BASE_OFFS + 0x10)

#define VIDC_CPU_IC_INTENACLEAR		(VIDC_CPU_IC_BASE_OFFS + 0x14)

#define VIDC_CPU_IC_SOFTINT			(VIDC_CPU_IC_BASE_OFFS + 0x18)

#define VIDC_CPU_IC_SOFTINT			(VIDC_CPU_IC_BASE_OFFS + 0x150)

#define VIDC_CPU_IC_SOFTINT_H2A_BMSK	0x8000

#define VIDC_CPU_IC_SOFTINT_H2A_SHFT	0xF

#define VIDC_CPU_IC_SOFTINT_H2A_SHFT	0x1

#define VIDC_CPU_IC_SOFTINTCLEAR	(VIDC_CPU_IC_BASE_OFFS + 0x1C)



/*
@@ -79,7 +79,7 @@ 
 * MODULE: vidc_wrapper

 * --------------------------------------------------------------------------

 */

#define VIDC_WRAPPER_BASE_OFFS		0x000E0000

#define VIDC_WRAPPER_BASE_OFFS		0x000B0000



#define VIDC_WRAPPER_HW_VERSION		(VIDC_WRAPPER_BASE_OFFS + 0x00)

#define VIDC_WRAPPER_HW_VERSION_MAJOR_VERSION_MASK  0x78000000