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Commit 1ac089f6 authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

drm/msm/sde: avoid fill-level calculation for QoS/danger/safe LUTs 



Add plane feature flag to avoid calculating the fill-levels
and add parsing code to get macrotile-qseed lut configs for
QoS/danger/safe.

Change-Id: If92f926b133466c329dcab7a29653a9a1370397f
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent 150e5aba

Documentation/devicetree/bindings/display/msm/sde.txt

+21 −4
Original line number Diff line number Diff line
@@ -352,8 +352,8 @@ Optional properties: 
				priority for realtime clients.

- qcom,sde-vbif-qos-nrt-remap:	This array is used to program vbif qos remapper register

				priority for non-realtime clients.

- qcom,sde-danger-lut:		A 4 cell property, with a format of <linear,

				tile, nrt, cwb>,

- qcom,sde-danger-lut:		Array of 5 cell property, with a format of

				<linear, tile, nrt, cwb, tile-qseed>,

				indicating the danger luts on sspp.

- qcom,sde-safe-lut-linear:	Array of 2 cell property, with a format of

				<fill level, lut> in ascending fill level
@@ -363,6 +363,11 @@ Optional properties: 
				<fill level, lut> in ascending fill level

				indicating the safe luts for macrotile format on sspp.

				Zero fill level on the last entry identifies the default lut.

- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of

				<fill level, lut> in ascending fill level

				indicating the safe luts for macrotile format

				with qseed3 on sspp.

				Zero fill level on the last entry identifies the default lut.

- qcom,sde-safe-lut-nrt:	Array of 2 cell property, with a format of

				<fill level, lut> in ascending fill level

				indicating the safe luts for nrt (e.g wfd) on sspp.
@@ -379,6 +384,11 @@ Optional properties: 
				<fill level, lut hi, lut lo> in ascending fill level

				indicating the qos luts for macrotile format on sspp.

				Zero fill level on the last entry identifies the default lut.

- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of

				<fill level, lut hi, lut lo> in ascending fill level

				indicating the qos luts for macrotile format

				with qseed3 enabled on sspp.

				Zero fill level on the last entry identifies the default lut.

- qcom,sde-qos-lut-nrt:		Array of 3 cell property, with a format of

				<fill level, lut hi, lut lo> in ascending fill level

				indicating the qos luts for nrt (e.g wfd) on sspp.
@@ -617,8 +627,13 @@ Example: 
    qcom,sde-wb-clk-ctrl = <0x2bc 16>;



    qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000

            0x00000000>;

    qcom,sde-safe-lut = <0xfffc 0xff00 0xffff 0xffff>;

            0x00000000 0x0000ffff>;

    qcom,sde-safe-lut-linear = <0 0xfff8>;

    qcom,sde-safe-lut-macrotile = <0 0xf000>;

    qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;

    qcom,sde-safe-lut-nrt = <0 0xffff>;

    qcom,sde-safe-lut-cwb = <0 0xffff>;



    qcom,sde-qos-lut-linear =

            <4 0x00000000 0x00000357>,

            <5 0x00000000 0x00003357>,
@@ -639,6 +654,8 @@ Example: 
            <13 0x00002233 0x44556677>,

            <14 0x00012233 0x44556677>,

            <0 0x00112233 0x44556677>;

    qcom,sde-qos-lut-macrotile-qseed =

            <0 0x00112233 0x66777777>;

    qcom,sde-qos-lut-nrt =

            <0 0x00000000 0x00000000>;

    qcom,sde-qos-lut-cwb =

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+28 −1
Original line number Diff line number Diff line
@@ -201,6 +201,8 @@ enum { 
	PERF_CDP_SETTING,

	PERF_CPU_MASK,

	PERF_CPU_DMA_LATENCY,

	PERF_QOS_LUT_MACROTILE_QSEED,

	PERF_SAFE_LUT_MACROTILE_QSEED,

	PERF_PROP_MAX,

};
@@ -497,6 +499,10 @@ static struct sde_prop_type sde_perf_prop[] = { 
	{PERF_CPU_MASK, "qcom,sde-qos-cpu-mask", false, PROP_TYPE_U32},

	{PERF_CPU_DMA_LATENCY, "qcom,sde-qos-cpu-dma-latency", false,

			PROP_TYPE_U32},

	{PERF_QOS_LUT_MACROTILE_QSEED, "qcom,sde-qos-lut-macrotile-qseed",

			false, PROP_TYPE_U32_ARRAY},

	{PERF_SAFE_LUT_MACROTILE_QSEED, "qcom,sde-safe-lut-macrotile-qseed",

			false, PROP_TYPE_U32_ARRAY},

};



static struct sde_prop_type sspp_prop[] = {
@@ -3133,6 +3139,18 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (rc)

		goto freeprop;



	rc = _validate_dt_entry(np,

			&sde_perf_prop[PERF_QOS_LUT_MACROTILE_QSEED], 1,

			&prop_count[PERF_QOS_LUT_MACROTILE_QSEED], NULL);

	if (rc)

		goto freeprop;



	rc = _validate_dt_entry(np,

			&sde_perf_prop[PERF_SAFE_LUT_MACROTILE_QSEED], 1,

			&prop_count[PERF_SAFE_LUT_MACROTILE_QSEED], NULL);

	if (rc)

		goto freeprop;



	rc = _read_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),

			prop_count, prop_exists, prop_value);

	if (rc)
@@ -3239,6 +3257,8 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
					PERF_SAFE_LUT_NRT,

			[SDE_QOS_LUT_USAGE_CWB] =

					PERF_SAFE_LUT_CWB,

			[SDE_QOS_LUT_USAGE_MACROTILE_QSEED] =

					PERF_SAFE_LUT_MACROTILE_QSEED,

		};

		const u32 entry_size = 2;

		int m, count;
@@ -3281,6 +3301,8 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
					PERF_QOS_LUT_NRT,

			[SDE_QOS_LUT_USAGE_CWB] =

					PERF_QOS_LUT_CWB,

			[SDE_QOS_LUT_USAGE_MACROTILE_QSEED] =

					PERF_QOS_LUT_MACROTILE_QSEED,

		};

		const u32 entry_size = 3;

		int m, count;
@@ -3575,10 +3597,15 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, 
	if (!sde_cfg)

		return -EINVAL;



	if (IS_SM8150_TARGET(hw_rev))

	if (IS_SM8150_TARGET(hw_rev)) {

		sde_cfg->sui_supported_blendstage =

			sde_cfg->max_mixer_blendstages - SDE_STAGE_0;



		for (i = 0; i < sde_cfg->sspp_count; i++)

			set_bit(SDE_SSPP_QOS_FL_NOCALC,

					&sde_cfg->sspp[i].features);

	}



	for (i = 0; i < sde_cfg->sspp_count; i++) {

		if (sde_cfg->sspp[i].sblk) {

			max_horz_deci = max(max_horz_deci,

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+3 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ enum { 
 * @SDE_SSPP_DGM_CSC         Support of color space conversion in DGM block

 * @SDE_SSPP_SEC_UI_ALLOWED   Allows secure-ui layers

 * @SDE_SSPP_BLOCK_SEC_UI    Blocks secure-ui layers

 * @SDE_SSPP_QOS_FL_NOCALC   Avoid fill level calculation for QoS/danger/safe

 * @SDE_SSPP_MAX             maximum value

 */

enum {
@@ -188,6 +189,7 @@ enum { 
	SDE_SSPP_DGM_CSC,

	SDE_SSPP_SEC_UI_ALLOWED,

	SDE_SSPP_BLOCK_SEC_UI,

	SDE_SSPP_QOS_FL_NOCALC,

	SDE_SSPP_MAX

};
@@ -450,6 +452,7 @@ enum sde_qos_lut_usage { 
	SDE_QOS_LUT_USAGE_MACROTILE,

	SDE_QOS_LUT_USAGE_NRT,

	SDE_QOS_LUT_USAGE_CWB,

	SDE_QOS_LUT_USAGE_MACROTILE_QSEED,

	SDE_QOS_LUT_USAGE_MAX,

};

drivers/gpu/drm/msm/sde/sde_plane.c

+9 −0
Original line number Diff line number Diff line
@@ -287,6 +287,9 @@ static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, 
	}



	psde = to_sde_plane(plane);

	if (psde->features & BIT(SDE_SSPP_QOS_FL_NOCALC))

		return 0;



	pstate = to_sde_plane_state(plane->state);

	rstate = &pstate->rot;

	fixed_buff_size = psde->pipe_sblk->pixel_ram_size;
@@ -405,6 +408,8 @@ static void _sde_plane_set_qos_lut(struct drm_plane *plane, 


		if (fmt && SDE_FORMAT_IS_LINEAR(fmt))

			lut_usage = SDE_QOS_LUT_USAGE_LINEAR;

		else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3))

			lut_usage = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;

		else

			lut_usage = SDE_QOS_LUT_USAGE_MACROTILE;

	}
@@ -469,6 +474,10 @@ static void _sde_plane_set_danger_lut(struct drm_plane *plane, 
			danger_lut = psde->catalog->perf.danger_lut_tbl

					[SDE_QOS_LUT_USAGE_LINEAR];

			lut_usage = SDE_QOS_LUT_USAGE_LINEAR;

		} else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {

			danger_lut = psde->catalog->perf.danger_lut_tbl

					[SDE_QOS_LUT_USAGE_MACROTILE_QSEED];

			lut_usage = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;

		} else {

			danger_lut = psde->catalog->perf.danger_lut_tbl

					[SDE_QOS_LUT_USAGE_MACROTILE];