Loading Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 331 SUBLEVEL = 334 EXTRAVERSION = NAME = Petit Gorille Loading arch/arm/xen/enlighten.c +2 −1 Original line number Diff line number Diff line Loading @@ -376,7 +376,8 @@ static int __init xen_guest_init(void) * for secondary CPUs as they are brought up. * For uniformity we use VCPUOP_register_vcpu_info even on cpu0. */ xen_vcpu_info = alloc_percpu(struct vcpu_info); xen_vcpu_info = __alloc_percpu(sizeof(struct vcpu_info), 1 << fls(sizeof(struct vcpu_info) - 1)); if (xen_vcpu_info == NULL) return -ENOMEM; Loading arch/powerpc/kernel/fpu.S +13 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,15 @@ #include <asm/export.h> #ifdef CONFIG_VSX #define __REST_1FPVSR(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ REST_FPR(n,base); \ b 3f; \ 2: REST_VSR(n,c,base); \ 3: #define __REST_32FPVSRS(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ Loading @@ -45,9 +54,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 2: SAVE_32VSRS(n,c,base); \ 3: #else #define __REST_1FPVSR(n,b,base) REST_FPR(n, base) #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) #endif #define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) Loading @@ -70,6 +81,7 @@ _GLOBAL(store_fp_state) SAVE_32FPVSRS(0, R4, R3) mffs fr0 stfd fr0,FPSTATE_FPSCR(r3) REST_1FPVSR(0, R4, R3) blr EXPORT_SYMBOL(store_fp_state) Loading Loading @@ -134,6 +146,7 @@ _GLOBAL(save_fpu) 2: SAVE_32FPVSRS(0, R4, R6) mffs fr0 stfd fr0,FPSTATE_FPSCR(r6) REST_1FPVSR(0, R4, R6) blr /* Loading arch/powerpc/kernel/trace/ftrace_64_mprofile.S +7 −2 Original line number Diff line number Diff line Loading @@ -41,6 +41,9 @@ _GLOBAL(ftrace_caller) /* Save the original return address in A's stack frame */ std r0,LRSAVE(r1) /* Create a minimal stack frame for representing B */ stdu r1, -STACK_FRAME_MIN_SIZE(r1) /* Create our stack frame + pt_regs */ stdu r1,-SWITCH_FRAME_SIZE(r1) Loading @@ -51,7 +54,7 @@ _GLOBAL(ftrace_caller) SAVE_10GPRS(22, r1) /* Save previous stack pointer (r1) */ addi r8, r1, SWITCH_FRAME_SIZE addi r8, r1, SWITCH_FRAME_SIZE+STACK_FRAME_MIN_SIZE std r8, GPR1(r1) /* Load special regs for save below */ Loading @@ -64,6 +67,8 @@ _GLOBAL(ftrace_caller) mflr r7 /* Save it as pt_regs->nip */ std r7, _NIP(r1) /* Also save it in B's stackframe header for proper unwind */ std r7, LRSAVE+SWITCH_FRAME_SIZE(r1) /* Save the read LR in pt_regs->link */ std r0, _LINK(r1) Loading Loading @@ -146,7 +151,7 @@ ftrace_call: ld r2, 24(r1) /* Pop our stack frame */ addi r1, r1, SWITCH_FRAME_SIZE addi r1, r1, SWITCH_FRAME_SIZE+STACK_FRAME_MIN_SIZE #ifdef CONFIG_LIVEPATCH /* Loading arch/powerpc/kernel/vector.S +2 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,7 @@ _GLOBAL(store_vr_state) mfvscr v0 li r4, VRSTATE_VSCR stvx v0, r4, r3 lvx v0, 0, r3 blr EXPORT_SYMBOL(store_vr_state) Loading Loading @@ -100,6 +101,7 @@ _GLOBAL(save_altivec) mfvscr v0 li r4,VRSTATE_VSCR stvx v0,r4,r7 lvx v0,0,r7 blr #ifdef CONFIG_VSX Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 331 SUBLEVEL = 334 EXTRAVERSION = NAME = Petit Gorille Loading
arch/arm/xen/enlighten.c +2 −1 Original line number Diff line number Diff line Loading @@ -376,7 +376,8 @@ static int __init xen_guest_init(void) * for secondary CPUs as they are brought up. * For uniformity we use VCPUOP_register_vcpu_info even on cpu0. */ xen_vcpu_info = alloc_percpu(struct vcpu_info); xen_vcpu_info = __alloc_percpu(sizeof(struct vcpu_info), 1 << fls(sizeof(struct vcpu_info) - 1)); if (xen_vcpu_info == NULL) return -ENOMEM; Loading
arch/powerpc/kernel/fpu.S +13 −0 Original line number Diff line number Diff line Loading @@ -27,6 +27,15 @@ #include <asm/export.h> #ifdef CONFIG_VSX #define __REST_1FPVSR(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ REST_FPR(n,base); \ b 3f; \ 2: REST_VSR(n,c,base); \ 3: #define __REST_32FPVSRS(n,c,base) \ BEGIN_FTR_SECTION \ b 2f; \ Loading @@ -45,9 +54,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ 2: SAVE_32VSRS(n,c,base); \ 3: #else #define __REST_1FPVSR(n,b,base) REST_FPR(n, base) #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) #endif #define REST_1FPVSR(n,c,base) __REST_1FPVSR(n,__REG_##c,__REG_##base) #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) Loading @@ -70,6 +81,7 @@ _GLOBAL(store_fp_state) SAVE_32FPVSRS(0, R4, R3) mffs fr0 stfd fr0,FPSTATE_FPSCR(r3) REST_1FPVSR(0, R4, R3) blr EXPORT_SYMBOL(store_fp_state) Loading Loading @@ -134,6 +146,7 @@ _GLOBAL(save_fpu) 2: SAVE_32FPVSRS(0, R4, R6) mffs fr0 stfd fr0,FPSTATE_FPSCR(r6) REST_1FPVSR(0, R4, R6) blr /* Loading
arch/powerpc/kernel/trace/ftrace_64_mprofile.S +7 −2 Original line number Diff line number Diff line Loading @@ -41,6 +41,9 @@ _GLOBAL(ftrace_caller) /* Save the original return address in A's stack frame */ std r0,LRSAVE(r1) /* Create a minimal stack frame for representing B */ stdu r1, -STACK_FRAME_MIN_SIZE(r1) /* Create our stack frame + pt_regs */ stdu r1,-SWITCH_FRAME_SIZE(r1) Loading @@ -51,7 +54,7 @@ _GLOBAL(ftrace_caller) SAVE_10GPRS(22, r1) /* Save previous stack pointer (r1) */ addi r8, r1, SWITCH_FRAME_SIZE addi r8, r1, SWITCH_FRAME_SIZE+STACK_FRAME_MIN_SIZE std r8, GPR1(r1) /* Load special regs for save below */ Loading @@ -64,6 +67,8 @@ _GLOBAL(ftrace_caller) mflr r7 /* Save it as pt_regs->nip */ std r7, _NIP(r1) /* Also save it in B's stackframe header for proper unwind */ std r7, LRSAVE+SWITCH_FRAME_SIZE(r1) /* Save the read LR in pt_regs->link */ std r0, _LINK(r1) Loading Loading @@ -146,7 +151,7 @@ ftrace_call: ld r2, 24(r1) /* Pop our stack frame */ addi r1, r1, SWITCH_FRAME_SIZE addi r1, r1, SWITCH_FRAME_SIZE+STACK_FRAME_MIN_SIZE #ifdef CONFIG_LIVEPATCH /* Loading
arch/powerpc/kernel/vector.S +2 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,7 @@ _GLOBAL(store_vr_state) mfvscr v0 li r4, VRSTATE_VSCR stvx v0, r4, r3 lvx v0, 0, r3 blr EXPORT_SYMBOL(store_vr_state) Loading Loading @@ -100,6 +101,7 @@ _GLOBAL(save_altivec) mfvscr v0 li r4,VRSTATE_VSCR stvx v0,r4,r7 lvx v0,0,r7 blr #ifdef CONFIG_VSX Loading