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Commit 1974a2a2 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: remove unnecessary debug message 



remnants from bring-up.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 88eadc31

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -56,7 +56,6 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) 




	/* Program MC. */

	/* Program MC. */

	/* Update configuration */

	/* Update configuration */

	DRM_INFO("%s -- in\n", __func__);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR),

		adev->mc.vram_start >> 18);

		adev->mc.vram_start >> 18);

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),

	WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR),

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+0 −19
Original line number Original line Diff line number Diff line
@@ -150,20 +150,6 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 
	}

	}

}

}





static void sdma_v4_0_print_ucode_regs(void *handle)

{

	int i;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	dev_info(adev->dev, "VEGA10 SDMA ucode registers\n");

	for (i = 0; i < adev->sdma.num_instances; i++) {

		dev_info(adev->dev, "  SDMA%d_UCODE_ADDR=0x%08X\n",

			 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR)));

		dev_info(adev->dev, "  SDMA%d_UCODE_CHECKSUM=0x%08X\n",

			 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM)));

	}

}



/**

/**

 * sdma_v4_0_init_microcode - load ucode images from disk

 * sdma_v4_0_init_microcode - load ucode images from disk

 *

 *
@@ -804,8 +790,6 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 
		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

	}

	}





	sdma_v4_0_print_ucode_regs(adev);



	return 0;

	return 0;

}

}
@@ -831,7 +815,6 @@ static int sdma_v4_0_start(struct amdgpu_device *adev) 
	}

	}





	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {

	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {

		DRM_INFO("Loading via direct write\n");

		r = sdma_v4_0_load_microcode(adev);

		r = sdma_v4_0_load_microcode(adev);

		if (r)

		if (r)

			return r;

			return r;
@@ -869,8 +852,6 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 
	u32 tmp;

	u32 tmp;

	u64 gpu_addr;

	u64 gpu_addr;





	DRM_INFO("In Ring test func\n");



	r = amdgpu_wb_get(adev, &index);

	r = amdgpu_wb_get(adev, &index);

	if (r) {

	if (r) {

		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);

		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);