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Commit 1840481f authored Feb 05, 2015 by Hoath, Nicholas Committed by Daniel Vetter Feb 13, 2015

drm/i915/gen9: Implement Wa4x4STCOptimizationDisable



Move Wa4x4STCOptimizationDisable to gen9_init_workarounds

v2: rebase

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent cac23df4

drivers/gpu/drm/i915/intel_pm.c

+0 −4

Original line number	Original line	Diff line number	Diff line
	@@ -64,10 +64,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) \|		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) \|
	GEN8_SDEUNIT_CLOCK_GATE_DISABLE);		GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
	}		}

	/* Wa4x4STCOptimizationDisable:skl */
	I915_WRITE(CACHE_MODE_1,
	_MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
	}		}

	static void i915_pineview_get_mem_freq(struct drm_device *dev)		static void i915_pineview_get_mem_freq(struct drm_device *dev)

drivers/gpu/drm/i915/intel_ringbuffer.c

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -902,6 +902,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
	GEN9_ENABLE_YV12_BUGFIX);		GEN9_ENABLE_YV12_BUGFIX);
	}		}

			/* Wa4x4STCOptimizationDisable:skl */
			WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);

	return 0;		return 0;
	}		}