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Commit 17b9b3b9 authored by Sascha Hauer's avatar Sascha Hauer Committed by Shawn Guo
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ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_sel 



Route the video PLL to the display interface clocks via the di_pre_sel
and di_sel muxes by default.

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Tested-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 4b2b4043

arch/arm/mach-imx/clk-imx6q.c

+9 −0
Original line number Diff line number Diff line
@@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
		clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);

	}



	clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);

	clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);

	clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);

	clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);

	clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);

	clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);

	clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);

	clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);



	/*

	 * The gpmi needs 100MHz frequency in the EDO/Sync mode,

	 * We can not get the 100MHz from the pll2_pfd0_352m.