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Commit 1463fba3 authored by Guoxiong Yan's avatar Guoxiong Yan Committed by Wei Xu
Browse files

clk: hix5hd2: add watchdog0 clocks 



hix5hd2 add watchdog0 clocks

Signed-off-by: default avatarGuoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: default avatarZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: default avatarWei Xu <xuwei5@hisilicon.com>
parent cc855dd9

drivers/clk/hisilicon/clk-hix5hd2.c

+5 −0
Original line number Diff line number Diff line
@@ -95,6 +95,11 @@ static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = { 
	{ HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },

	{ HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",

		 CLK_SET_RATE_PARENT, 0x120, 0, 0, },

	/* wdg0 */

	{ HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",

		CLK_SET_RATE_PARENT, 0x178, 0, 0, },

	{ HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",

		CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },

};



enum hix5hd2_clk_type {

include/dt-bindings/clock/hix5hd2-clock.h

+2 −0
Original line number Diff line number Diff line
@@ -60,6 +60,8 @@ 
#define HIX5HD2_SD_CIU_CLK		136

#define HIX5HD2_SD_BIU_CLK		137

#define HIX5HD2_SD_CIU_RST		138

#define HIX5HD2_WDG0_CLK		139

#define HIX5HD2_WDG0_RST		140



/* complex */

#define HIX5HD2_MAC0_CLK		192