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Commit 14155c76 authored by Hardik Kantilal Patel's avatar Hardik Kantilal Patel Committed by Gerrit - the friendly Code Review server
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icnss: Enable SMMU Stage 1 based on DT. 



As SMMU stage 1 is not supported for all target. So
Enable SMMU Stage 1 based on DT parameter.

CRs-fixed: 2078803
Change-Id: Ieebbf830cf3cc2a29ffafcceac38818c8c3eeb30
Signed-off-by: default avatarHardik Kantilal Patel <hkpatel@codeaurora.org>
parent 03ade87f

drivers/soc/qcom/icnss.c

+22 −8
Original line number Diff line number Diff line
@@ -1909,6 +1909,7 @@ static int icnss_smmu_init(struct icnss_priv *priv) 
	struct dma_iommu_mapping *mapping;

	int atomic_ctx = 1;

	int s1_bypass = 1;

	int fast = 1;

	int ret = 0;



	icnss_pr_dbg("Initializing SMMU\n");
@@ -1922,7 +1923,17 @@ static int icnss_smmu_init(struct icnss_priv *priv) 
		goto map_fail;

	}



	if (!priv->bypass_s1_smmu) {

	if (priv->bypass_s1_smmu) {

		ret = iommu_domain_set_attr(mapping->domain,

					    DOMAIN_ATTR_S1_BYPASS,

					    &s1_bypass);

		if (ret < 0) {

			icnss_pr_err("Set s1_bypass attribute failed, err = %d\n",

				     ret);

			goto set_attr_fail;

		}

		icnss_pr_dbg("SMMU S1 BYPASS\n");

	} else {

		ret = iommu_domain_set_attr(mapping->domain,

					    DOMAIN_ATTR_ATOMIC,

					    &atomic_ctx);
@@ -1931,15 +1942,18 @@ static int icnss_smmu_init(struct icnss_priv *priv) 
				     ret);

			goto set_attr_fail;

		}

	}

		icnss_pr_dbg("SMMU ATTR ATOMIC\n");



		ret = iommu_domain_set_attr(mapping->domain,

				    DOMAIN_ATTR_S1_BYPASS,

				    &s1_bypass);

					    DOMAIN_ATTR_FAST,

					    &fast);

		if (ret < 0) {

		icnss_pr_err("Set s1_bypass attribute failed, err = %d\n", ret);

			icnss_pr_err("Set fast map attribute failed, err = %d\n",

				     ret);

			goto set_attr_fail;

		}

		icnss_pr_dbg("SMMU FAST map set\n");

	}



	ret = arm_iommu_attach_device(&priv->pdev->dev, mapping);

	if (ret < 0) {