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Commit 13ec32f4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

ARM: ixp4xx: use __iomem pointers for MMIO 



ARM is moving to stricter checks on readl/write functions,
so we need to use the correct types everywhere.

At the moment, this patch conflicts with other patches in linux-next,
need to sort this out.

Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 3c65c6ba

arch/arm/mach-ixp4xx/common.c

+4 −4
Original line number Diff line number Diff line
@@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx; 
 *************************************************************************/

static struct map_desc ixp4xx_io_desc[] __initdata = {

	{	/* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */

		.virtual	= IXP4XX_PERIPHERAL_BASE_VIRT,

		.virtual	= (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),

		.length		= IXP4XX_PERIPHERAL_REGION_SIZE,

		.type		= MT_DEVICE

	}, {	/* Expansion Bus Config Registers */

		.virtual	= IXP4XX_EXP_CFG_BASE_VIRT,

		.virtual	= (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),

		.length		= IXP4XX_EXP_CFG_REGION_SIZE,

		.type		= MT_DEVICE

	}, {	/* PCI Registers */

		.virtual	= IXP4XX_PCI_CFG_BASE_VIRT,

		.virtual	= (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),

		.length		= IXP4XX_PCI_CFG_REGION_SIZE,

		.type		= MT_DEVICE

	},

#ifdef CONFIG_DEBUG_LL

	{	/* Debug UART mapping */

		.virtual	= IXP4XX_DEBUG_UART_BASE_VIRT,

		.virtual	= (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,

		.pfn		= __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),

		.length		= IXP4XX_DEBUG_UART_REGION_SIZE,

		.type		= MT_DEVICE

arch/arm/mach-ixp4xx/include/mach/cpu.h

+3 −2
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#ifndef __ASM_ARCH_CPU_H__

#define __ASM_ARCH_CPU_H__



#include <linux/io.h>

#include <asm/cputype.h>



/* Processor id value in CP15 Register 0 */
@@ -37,7 +38,7 @@ 


static inline u32 ixp4xx_read_feature_bits(void)

{

	u32 val = ~*IXP4XX_EXP_CFG2;

	u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);



	if (cpu_is_ixp42x_rev_a0())

		return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void) 


static inline void ixp4xx_write_feature_bits(u32 value)

{

	*IXP4XX_EXP_CFG2 = ~value;

	__raw_writel(~value, IXP4XX_EXP_CFG2);

}



#endif  /* _ASM_ARCH_CPU_H */

arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h

+5 −5
Original line number Diff line number Diff line
@@ -49,21 +49,21 @@ 
 * Expansion BUS Configuration registers

 */

#define IXP4XX_EXP_CFG_BASE_PHYS	(0xC4000000)

#define IXP4XX_EXP_CFG_BASE_VIRT	(0xFFBFE000)

#define IXP4XX_EXP_CFG_BASE_VIRT	IOMEM(0xFFBFE000)

#define IXP4XX_EXP_CFG_REGION_SIZE	(0x00001000)



/*

 * PCI Config registers

 */

#define IXP4XX_PCI_CFG_BASE_PHYS	(0xC0000000)

#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFF000)

#define	IXP4XX_PCI_CFG_BASE_VIRT	IOMEM(0xFFBFF000)

#define IXP4XX_PCI_CFG_REGION_SIZE	(0x00001000)



/*

 * Peripheral space

 */

#define IXP4XX_PERIPHERAL_BASE_PHYS	(0xC8000000)

#define IXP4XX_PERIPHERAL_BASE_VIRT	(0xFFBEB000)

#define IXP4XX_PERIPHERAL_BASE_VIRT	IOMEM(0xFFBEB000)

#define IXP4XX_PERIPHERAL_REGION_SIZE	(0x00013000)



/*
@@ -73,7 +73,7 @@ 
 * aligned so that it * can be used with the low-level debug code.

 */

#define	IXP4XX_DEBUG_UART_BASE_PHYS	(0xC8000000)

#define	IXP4XX_DEBUG_UART_BASE_VIRT	(0xffb00000)

#define	IXP4XX_DEBUG_UART_BASE_VIRT	IOMEM(0xffb00000)

#define	IXP4XX_DEBUG_UART_REGION_SIZE	(0x00001000)



#define IXP4XX_EXP_CS0_OFFSET	0x00
@@ -92,7 +92,7 @@ 
/*

 * Expansion Bus Controller registers.

 */

#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))

#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))



#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)

#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)