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Unverified Commit 13838c11 authored by Mukunda, Vijendar's avatar Mukunda, Vijendar Committed by Mark Brown
Browse files

ASoC: amd: fixed checkpatch pl warnings 



fixed checkpatch pl warnings.

Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 112c60b3

sound/soc/amd/acp-pcm-dma.c

+141 −118
Original line number Diff line number Diff line
@@ -130,7 +130,8 @@ static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 
	writel(val, acp_mmio + (reg * 4));

}



/* Configure a given dma channel parameters - enable/disable,

/*

 * Configure a given dma channel parameters - enable/disable,

 * number of descriptors, priority

 */

static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
@@ -149,7 +150,8 @@ static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 
			& dscr_strt_idx),

			acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);



	/* program a DMA channel with the number of descriptors to be

	/*

	 * program a DMA channel with the number of descriptors to be

	 * processed in the transfer

	 */

	acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
@@ -180,13 +182,15 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 
	acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);

}



/* Initialize the DMA descriptor information for transfer between

/*

 * Initialize the DMA descriptor information for transfer between

 * system memory <-> ACP SRAM

 */

static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,

					u32 size, int direction, u32 pte_offset,

					u16 ch, u32 sram_bank,

					u16 dma_dscr_idx, u32 asic_type)

					   u32 size, int direction,

					   u32 pte_offset, u16 ch,

					   u32 sram_bank, u16 dma_dscr_idx,

					   u32 asic_type)

{

	u16 i;

	acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
@@ -201,12 +205,12 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 
			switch (asic_type) {

			case CHIP_STONEY:

				dmadscr[i].xfer_val |=

				(ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM  << 16) |

				(ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM  << 16) |

				(size / 2);

				break;

			default:

				dmadscr[i].xfer_val |=

				(ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM  << 16) |

				(ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM  << 16) |

				(size / 2);

			}

		} else {
@@ -219,13 +223,13 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 
			case CHIP_STONEY:

				dmadscr[i].xfer_val |=

				BIT(22) |

				(ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) |

				(ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |

				(size / 2);

				break;

			default:

				dmadscr[i].xfer_val |=

				BIT(22) |

				(ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) |

				(ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |

				(size / 2);

			}

		}
@@ -238,7 +242,8 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 
			       ACP_DMA_PRIORITY_LEVEL_NORMAL);

}



/* Initialize the DMA descriptor information for transfer between

/*

 * Initialize the DMA descriptor information for transfer between

 * ACP SRAM <-> I2S

 */

static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
@@ -246,7 +251,6 @@ static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 
					   u16 destination, u16 ch,

					   u16 dma_dscr_idx, u32 asic_type)

{



	u16 i;

	acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
@@ -349,8 +353,8 @@ static void config_acp_dma(void __iomem *acp_mmio, 


	/* Configure System memory <-> ACP SRAM DMA descriptors */

	set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size,

				       audio_config->direction, pte_offset,

					ch1, sram_bank, dma_dscr_idx, asic_type);

				       audio_config->direction, pte_offset, ch1,

				       sram_bank, dma_dscr_idx, asic_type);



	if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK)

		dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
@@ -375,7 +379,8 @@ static void acp_dma_start(void __iomem *acp_mmio, 
	/* Invalidating the DAGB cache */

	acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);



	/* configure the DMA channel and start the DMA transfer

	/*

	 * configure the DMA channel and start the DMA transfer

	 * set dmachrun bit to start the transfer and enable the

	 * interrupt on completion of the dma transfer

	 */
@@ -410,7 +415,8 @@ static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 


	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);



	/* clear the dma control register fields before writing zero

	/*

	 * clear the dma control register fields before writing zero

	 * in reset bit

	 */

	dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
@@ -420,7 +426,8 @@ static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 
	dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);



	if (dma_ch_sts & BIT(ch_num)) {

		/* set the reset bit for this channel to stop the dma

		/*

		 * set the reset bit for this channel to stop the dma

		 *  transfer

		 */

		dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
@@ -431,7 +438,8 @@ static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 
	while (true) {

		dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);

		if (!(dma_ch_sts & BIT(ch_num))) {

			/* clear the reset flag after successfully stopping

			/*

			 * clear the reset flag after successfully stopping

			 * the dma transfer and break from the loop

			 */

			dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
@@ -568,7 +576,8 @@ static int acp_init(void __iomem *acp_mmio, u32 asic_type) 
	acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,

		      acp_mmio, mmACP_EXTERNAL_INTR_CNTL);



       /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.

       /*

	* When ACP_TILE_P1 is turned on, all SRAM banks get turned on.

	* Now, turn off all of them. This can't be done in 'poweron' of

	* ACP pm domain, as this requires ACP to be initialized.

	* For Stoney, Memory gating is disabled,i.e SRAM Banks
@@ -606,7 +615,7 @@ static int acp_deinit(void __iomem *acp_mmio) 
		}

		udelay(100);

	}

	/** Disable ACP clock */

	/* Disable ACP clock */

	val = acp_reg_read(acp_mmio, mmACP_CONTROL);

	val &= ~ACP_CONTROL__ClkEn_MASK;

	acp_reg_write(val, acp_mmio, mmACP_CONTROL);
@@ -695,11 +704,12 @@ static int acp_dma_open(struct snd_pcm_substream *substream) 
	int ret = 0;

	struct snd_pcm_runtime *runtime = substream->runtime;

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);

	struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);

	struct audio_substream_data *adata =

		kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);

	if (adata == NULL)

	if (!adata)

		return -ENOMEM;



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
@@ -731,7 +741,8 @@ static int acp_dma_open(struct snd_pcm_substream *substream) 
	adata->acp_mmio = intr_data->acp_mmio;

	runtime->private_data = adata;



	/* Enable ACP irq, when neither playback or capture streams are

	/*

	 * Enable ACP irq, when neither playback or capture streams are

	 * active by the time when a new stream is being opened.

	 * This enablement is not required for another stream, if current

	 * stream is not closed
@@ -741,7 +752,8 @@ static int acp_dma_open(struct snd_pcm_substream *substream) 


	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

		intr_data->play_i2ssp_stream = substream;

		/* For Stoney, Memory gating is disabled,i.e SRAM Banks

		/*

		 * For Stoney, Memory gating is disabled,i.e SRAM Banks

		 * won't be turned off. The default state for SRAM banks is ON.

		 * Setting SRAM bank state code skipped for STONEY platform.

		 */
@@ -772,7 +784,8 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, 
	struct snd_pcm_runtime *runtime;

	struct audio_substream_data *rtd;

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);

	struct audio_drv_data *adata = dev_get_drvdata(component->dev);



	runtime = substream->runtime;
@@ -782,12 +795,14 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, 
		return -EINVAL;



	if (adata->asic_type == CHIP_STONEY) {

		val = acp_reg_read(adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN);

		val = acp_reg_read(adata->acp_mmio,

				   mmACP_I2S_16BIT_RESOLUTION_EN);

		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)

			val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;

		else

			val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;

		acp_reg_write(val, adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN);

		acp_reg_write(val, adata->acp_mmio,

			      mmACP_I2S_16BIT_RESOLUTION_EN);

	}

	size = params_buffer_bytes(params);

	status = snd_pcm_lib_malloc_pages(substream, size);
@@ -797,7 +812,7 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream, 
	memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));

	pg = virt_to_page(substream->dma_buffer.area);



	if (pg != NULL) {

	if (pg) {

		acp_set_sram_bank_state(rtd->acp_mmio, 0, true);

		/* Save for runtime private data */

		rtd->pg = pg;
@@ -910,7 +925,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 
	struct snd_pcm_runtime *runtime = substream->runtime;

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct audio_substream_data *rtd = runtime->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);



	if (!rtd)

		return -EINVAL;
@@ -949,7 +965,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 
	case SNDRV_PCM_TRIGGER_STOP:

	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:

	case SNDRV_PCM_TRIGGER_SUSPEND:

		/* Need to stop only circular DMA channels :

		/*

		 * Need to stop only circular DMA channels :

		 * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular

		 * channels will stopped automatically after its transfer

		 * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
@@ -970,7 +987,6 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 
		break;

	default:

		ret = -EINVAL;



	}

	return ret;

}
@@ -978,7 +994,8 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 
static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)

{

	int ret;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME);

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,

								    DRV_NAME);

	struct audio_drv_data *adata = dev_get_drvdata(component->dev);



	switch (adata->asic_type) {
@@ -1007,14 +1024,16 @@ static int acp_dma_close(struct snd_pcm_substream *substream) 
	struct snd_pcm_runtime *runtime = substream->runtime;

	struct audio_substream_data *rtd = runtime->private_data;

	struct snd_soc_pcm_runtime *prtd = substream->private_data;

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME);

	struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,

								    DRV_NAME);

	struct audio_drv_data *adata = dev_get_drvdata(component->dev);



	kfree(rtd);



	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {

		adata->play_i2ssp_stream = NULL;

		/* For Stoney, Memory gating is disabled,i.e SRAM Banks

		/*

		 * For Stoney, Memory gating is disabled,i.e SRAM Banks

		 * won't be turned off. The default state for SRAM banks is ON.

		 * Setting SRAM bank state code skipped for STONEY platform.

		 * added condition checks for Carrizo platform only
@@ -1033,7 +1052,8 @@ static int acp_dma_close(struct snd_pcm_substream *substream) 
		}

	}



	/* Disable ACP irq, when the current stream is being closed and

	/*

	 * Disable ACP irq, when the current stream is being closed and

	 * another stream is also not active.

	 */

	if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream)
@@ -1054,7 +1074,7 @@ static const struct snd_pcm_ops acp_dma_ops = { 
	.prepare = acp_dma_prepare,

};



static struct snd_soc_component_driver acp_asoc_platform = {

static const struct snd_soc_component_driver acp_asoc_platform = {

	.name = DRV_NAME,

	.ops = &acp_dma_ops,

	.pcm_new = acp_dma_new,
@@ -1074,7 +1094,7 @@ static int acp_audio_probe(struct platform_device *pdev) 


	audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),

				      GFP_KERNEL);

	if (audio_drv_data == NULL)

	if (!audio_drv_data)

		return -ENOMEM;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1082,7 +1102,8 @@ static int acp_audio_probe(struct platform_device *pdev) 
	if (IS_ERR(audio_drv_data->acp_mmio))

		return PTR_ERR(audio_drv_data->acp_mmio);



	/* The following members gets populated in device 'open'

	/*

	 * The following members gets populated in device 'open'

	 * function. Till then interrupts are disabled in 'acp_init'

	 * and device doesn't generate any interrupts.

	 */
@@ -1154,7 +1175,8 @@ static int acp_pcm_resume(struct device *dev) 
	}



	if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {

		/* For Stoney, Memory gating is disabled,i.e SRAM Banks

		/*

		 * For Stoney, Memory gating is disabled,i.e SRAM Banks

		 * won't be turned off. The default state for SRAM banks is ON.

		 * Setting SRAM bank state code skipped for STONEY platform.

		 */
@@ -1167,7 +1189,8 @@ static int acp_pcm_resume(struct device *dev) 
			       adata->play_i2ssp_stream->runtime->private_data,

			       adata->asic_type);

	}

	if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) {

	if (adata->capture_i2ssp_stream &&

	    adata->capture_i2ssp_stream->runtime) {

		if (adata->asic_type != CHIP_STONEY) {

			for (bank = 5; bank <= 8; bank++)

				acp_set_sram_bank_state(adata->acp_mmio, bank,

sound/soc/amd/acp.h

+12 −10
Original line number Diff line number Diff line
@@ -115,21 +115,23 @@ enum { 
};



enum {

	ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION = 0x0,

	ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC = 0x1,

	ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM = 0x8,

	ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM = 0x9,

	ACP_DMA_ATTRIBUTES_FORCE_SIZE = 0xF

	ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION = 0x0,

	ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC = 0x1,

	ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM = 0x8,

	ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM = 0x9,

	ACP_DMA_ATTR_FORCE_SIZE = 0xF

};



typedef struct acp_dma_dscr_transfer {

	/* Specifies the source memory location for the DMA data transfer. */

	u32 src;

	/* Specifies the destination memory location to where the data will

	/*

	 * Specifies the destination memory location to where the data will

	 * be transferred.

	 */

	u32 dest;

	/* Specifies the number of bytes need to be transferred

	/*

	 * Specifies the number of bytes need to be transferred

	 * from source to destination memory.Transfer direction & IOC enable

	 */

	u32 xfer_val;