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Commit 101c6fee authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher
Browse files

drm/amdgpu: add vcn enc rings 



Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3639f7d8

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c

+5 −0
Original line number Diff line number Diff line
@@ -126,6 +126,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) 


int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)

{

	int i;



	kfree(adev->vcn.saved_bo);



	amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
@@ -138,6 +140,9 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev) 


	amdgpu_ring_fini(&adev->vcn.ring_dec);



	for (i = 0; i < adev->vcn.num_enc_rings; ++i)

		amdgpu_ring_fini(&adev->vcn.ring_enc[i]);



	release_firmware(adev->vcn.fw);



	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ struct amdgpu_vcn { 
	struct amdgpu_irq_src	irq;

	struct amd_sched_entity entity_dec;

	struct amd_sched_entity entity_enc;

	uint32_t                srbm_soft_reset;

	unsigned		num_enc_rings;

};



int amdgpu_vcn_sw_init(struct amdgpu_device *adev);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+27 −1
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ static int vcn_v1_0_early_init(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	adev->vcn.num_enc_rings = 2;



	vcn_v1_0_set_dec_ring_funcs(adev);

	vcn_v1_0_set_irq_funcs(adev);
@@ -67,7 +69,7 @@ static int vcn_v1_0_early_init(void *handle) 
static int vcn_v1_0_sw_init(void *handle)

{

	struct amdgpu_ring *ring;

	int r;

	int i, r;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* VCN TRAP */
@@ -86,6 +88,16 @@ static int vcn_v1_0_sw_init(void *handle) 
	ring = &adev->vcn.ring_dec;

	sprintf(ring->name, "vcn_dec");

	r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);

	if (r)

		return r;



	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {

		ring = &adev->vcn.ring_enc[i];

		sprintf(ring->name, "vcn_enc%d", i);

		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);

		if (r)

			return r;

	}



	return r;

}
@@ -401,6 +413,20 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) 
	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,

			~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);



	ring = &adev->vcn.ring_enc[0];

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);



	ring = &adev->vcn.ring_enc[1];

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

	WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);



	return 0;

}