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Commit 0fc0708a authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O 



The dma_cache_wback_inv function performs exactly as is required here,
unless the system has coherent I/O in which case it's a no-op. Call the
underlying cache writeback functions directly, which is arguably clearer
anyway given that the code doesn't actually have anything to do with
DMA in a strict sense.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7282/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c90e49f2

arch/mips/kernel/smp-cps.c

+7 −3
Original line number Diff line number Diff line
@@ -14,13 +14,14 @@ 
#include <linux/smp.h>

#include <linux/types.h>



#include <asm/cacheflush.h>

#include <asm/bcache.h>

#include <asm/gic.h>

#include <asm/mips-cm.h>

#include <asm/mips-cpc.h>

#include <asm/mips_mt.h>

#include <asm/mipsregs.h>

#include <asm/pm-cps.h>

#include <asm/r4kcache.h>

#include <asm/smp-cps.h>

#include <asm/time.h>

#include <asm/uasm.h>
@@ -132,8 +133,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) 
	entry_code = (u32 *)&mips_cps_core_entry;

	UASM_i_LA(&entry_code, 3, (long)mips_cm_base);

	uasm_i_addiu(&entry_code, 16, 0, cca);

	dma_cache_wback_inv((unsigned long)&mips_cps_core_entry,

	blast_dcache_range((unsigned long)&mips_cps_core_entry,

			   (unsigned long)entry_code);

	bc_wback_inv((unsigned long)&mips_cps_core_entry,

		     (void *)entry_code - (void *)&mips_cps_core_entry);

	__sync();



	/* Allocate core boot configuration structs */

	mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),