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Commit 0faac84e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: Enable GCC clock driver for QCS405"

parents 5768dfb5 3ee9a1e3

arch/arm/configs/qcs405-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -311,6 +311,7 @@ CONFIG_STAGING=y 
CONFIG_ASHMEM=y

CONFIG_ION=y

CONFIG_COMMON_CLK_QCOM=y

CONFIG_MDM_GCC_QCS405=y

CONFIG_HWSPINLOCK=y

CONFIG_MAILBOX=y

CONFIG_QCOM_SMEM=y

arch/arm/configs/qcs405_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -321,6 +321,7 @@ CONFIG_STAGING=y 
CONFIG_ASHMEM=y

CONFIG_ION=y

CONFIG_COMMON_CLK_QCOM=y

CONFIG_MDM_GCC_QCS405=y

CONFIG_HWSPINLOCK=y

CONFIG_MAILBOX=y

CONFIG_QCOM_LAZY_MAPPING=y

arch/arm64/configs/qcs405-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -312,6 +312,7 @@ CONFIG_UIO=y 
CONFIG_STAGING=y

CONFIG_ASHMEM=y

CONFIG_ION=y

CONFIG_MDM_GCC_QCS405=y

CONFIG_HWSPINLOCK=y

CONFIG_MAILBOX=y

CONFIG_IOMMU_IO_PGTABLE_LPAE=y

arch/arm64/configs/qcs405_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -324,6 +324,7 @@ CONFIG_UIO=y 
CONFIG_STAGING=y

CONFIG_ASHMEM=y

CONFIG_ION=y

CONFIG_MDM_GCC_QCS405=y

CONFIG_HWSPINLOCK=y

CONFIG_MAILBOX=y

CONFIG_IOMMU_IO_PGTABLE_LPAE=y