Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0f7dafd4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux 

Pull clock subsystem fixes from Mike Turquette:
 "A mix of small fixes affecting mostly ARM platforms as well as a
  discrete clock expander chip.  Most fixes are corrections to lousy
  clock data of one form or another."

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
  clk: mxs: Include clk mxs header file
  clk: vt8500: Fix unbalanced spinlock in vt8500_dclk_set_rate()
  clk: si5351: Set initial clkout rate when defined in platform data.
  clk: si5351: Fix clkout rate computation.
  clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks
  clk: ux500: clk-sysctrl: handle clocks with no parents
  clk: ux500: Provide device enumeration number suffix for SMSC911x
parents c361cb59 d68c3805

drivers/clk/clk-si5351.c

+11 −1
Original line number Diff line number Diff line
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw, 
	unsigned char reg;

	unsigned char rdiv;



	if (hwdata->num > 5)

	if (hwdata->num <= 5)

		reg = si5351_msynth_params_address(hwdata->num) + 2;

	else

		reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client, 
			return -EINVAL;

		}

		drvdata->onecell.clks[n] = clk;



		/* set initial clkout rate */

		if (pdata->clkout[n].rate != 0) {

			int ret;

			ret = clk_set_rate(clk, pdata->clkout[n].rate);

			if (ret != 0) {

				dev_err(&client->dev, "Cannot set rate : %d\n",

					ret);

			}

		}

	}



	ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,

drivers/clk/clk-vt8500.c

+1 −1
Original line number Diff line number Diff line
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 
	writel(divisor, cdev->div_reg);

	vt8500_pmc_wait_busy();



	spin_lock_irqsave(cdev->lock, flags);

	spin_unlock_irqrestore(cdev->lock, flags);



	return 0;

}

drivers/clk/mxs/clk-imx28.c

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
 */



#include <linux/clk.h>

#include <linux/clk/mxs.h>

#include <linux/clkdev.h>

#include <linux/err.h>

#include <linux/init.h>

drivers/clk/samsung/clk-exynos4.c

+4 −2
Original line number Diff line number Diff line
@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { 
	GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),

	GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),

	GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),

	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),

	GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,

			CLK_IGNORE_UNUSED, 0),

	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),

	GATE(smmu_rotator, "smmu_rotator", "aclk200",

			E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { 
	GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),

	GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),

	GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),

	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),

	GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,

			CLK_IGNORE_UNUSED, 0),

	GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),

	GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",

			SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),

drivers/clk/ux500/clk-sysctrl.c

+7 −1
Original line number Diff line number Diff line
@@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev, 
		return ERR_PTR(-ENOMEM);

	}



	for (i = 0; i < num_parents; i++) {

	/* set main clock registers */

	clk->reg_sel[0] = reg_sel[0];

	clk->reg_bits[0] = reg_bits[0];

	clk->reg_mask[0] = reg_mask[0];



	/* handle clocks with more than one parent */

	for (i = 1; i < num_parents; i++) {

		clk->reg_sel[i] = reg_sel[i];

		clk->reg_bits[i] = reg_bits[i];

		clk->reg_mask[i] = reg_mask[i];