Merge "ARM: dts: msm: Add NPU device configuration for SA8195P" (0f7bea89) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sa8195p.dtsi

+199 −0

Original line number	Diff line number	Diff line
		@@ -18,6 +18,7 @@
		#include "sm8150-v2-camera.dtsi"
		#include "sa8155-camera-sensor.dtsi"
		#include "sa8195p-pcie.dtsi"
		#include "sm8150-npu.dtsi"

		/ {
		model = "Qualcomm Technologies, Inc. SA8195P";
		@@ -184,6 +185,50 @@
		<760000000 0 0>;
		clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
		};

		npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
		};

		npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x9960300 0x300>, <0x9960200 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&npu_npu_ddr_bw>;
		qcom,count-unit = <0x10000>;
		};

		qmp_npu0: qcom,qmp-npu-low@9818000 {
		compatible = "qcom,qmp-mbox";
		reg = <0x9818000 0x8000>, <0x9901008 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x12>;
		interrupts = <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;

		label = "npu_qmp_low";
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
		};

		qmp_npu1: qcom,qmp-npu-high@9818000 {
		compatible = "qcom,qmp-mbox";
		reg = <0x9818000 0x8000>, <0x9901008 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x14>;
		interrupts = <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>;

		label = "npu_qmp_high";
		priority = <1>;
		mbox-desc-offset = <0x2000>;
		#mbox-cells = <1>;
		};
		};

		&usb1 {
		@@ -472,3 +517,157 @@
		};
		};
		};

		&msm_npu {
		iommus = <&apps_smmu 0x1481 0x400>, <&apps_smmu 0x1081 0x400>;
		qcom,npu-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,npu-pwrlevels";
		initial-pwrlevel = <5>;
		qcom,npu-pwrlevel@0 {
		reg = <0>;
		vreg = <1>;
		clk-freq = <0
		0
		0
		100000000
		300000000
		300000000
		19200000
		150000000
		100000000
		37500000
		19200000
		60000000
		100000000
		19200000
		19200000
		0
		19200000
		300000000
		19200000
		19200000>;
		};
		qcom,npu-pwrlevel@1 {
		reg = <1>;
		vreg = <2>;
		clk-freq = <0
		0
		0
		150000000
		400000000
		400000000
		37500000
		200000000
		150000000
		75000000
		19200000
		120000000
		150000000
		19200000
		19200000
		0
		19200000
		400000000
		19200000
		19200000>;
		};
		qcom,npu-pwrlevel@2 {
		reg = <2>;
		vreg = <3>;
		clk-freq = <0
		0
		0
		200000000
		487000000
		487000000
		37500000
		300000000
		200000000
		150000000
		19200000
		240000000
		200000000
		19200000
		19200000
		0
		19200000
		487000000
		19200000
		19200000>;
		};
		qcom,npu-pwrlevel@3 {
		reg = <3>;
		vreg = <4>;
		clk-freq = <0
		0
		0
		300000000
		652000000
		652000000
		75000000
		403000000
		300000000
		150000000
		19200000
		240000000
		300000000
		19200000
		19200000
		0
		19200000
		652000000
		19200000
		19200000>;
		};
		qcom,npu-pwrlevel@4 {
		reg = <4>;
		vreg = <6>;
		clk-freq = <0
		0
		0
		400000000
		811000000
		811000000
		75000000
		533000000
		400000000
		150000000
		19200000
		300000000
		400000000
		19200000
		19200000
		0
		19200000
		811000000
		19200000
		19200000>;
		};
		qcom,npu-pwrlevel@5 {
		reg = <5>;
		vreg = <7>;
		clk-freq = <0
		0
		0
		400000000
		908000000
		908000000
		75000000
		533000000
		400000000
		150000000
		19200000
		300000000
		400000000
		19200000
		19200000
		0
		19200000
		908000000
		19200000
		19200000>;
		};
		};
		};