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Commit 0f55c839 authored Oct 16, 2019 by Da Hoon Pyun Committed by Gerrit - the friendly Code Review server Oct 17, 2019

ARM: dts: msm: Add npu mailbox controller for atoll



The mailbox controller implemented in NPU works as a bridge
between ipcc_mproc mailbox controller and its clients. It is
required because npu driver needs to control when IPCC irq can
be sent to NPUQ6.

Change-Id: I998c66c55ce0d959a3fe0dc382d2bbb9ccbe8e84
Signed-off-by: Da Hoon Pyun <dpyun@codeaurora.org>

parent 216c77f4

arch/arm64/boot/dts/qcom/atoll-npu.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -61,6 +61,10 @@
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		#cooling-cells = <2>;
		mboxes = <&apcs_glb2 4>,
		<&apcs_glb2 6>;
		mbox-names = "glink", "smp2p";
		#mbox-cells = <1>;
		qcom,npubw-devs = <&npu_npu_ddr_bw>;
		qcom,npubw-dev-names = "ddr_bw";
		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;

arch/arm64/boot/dts/qcom/atoll.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -2263,7 +2263,7 @@
		glink_npu: npu {
		transport = "smem";
		qcom,remote-pid = <10>;
		mboxes = <&apcs_glb2 4>;
		mboxes = <&msm_npu 4>;
		mbox-names = "npu_smem";
		interrupts = <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;