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Commit 0e626b32 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add QUPv3 and USB support for SA6155 VM"

parents 1c5bd0d5 dcee0ac6

arch/arm64/boot/dts/qcom/sa6155p-vm-qupv3.dtsi

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/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/*

	 * QUPv3 North & South Instances

	 * North 0 : SE 4

	 * North 1 : SE 5

	 * North 2 : SE 6

	 * North 3 : SE 7

	 * South 0 : SE 0

	 * South 1 : SE 1

	 * South 2 : SE 2

	 * South 3 : SE 3

	 */



	/* QUPv3 South Instances */

	qupv3_0: qcom,qupv3_0_geni_se@8c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x8c0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0xc3 0x0>;

		};

	};



	/* Debug UART Instance for CDP/MTP platform */

	qupv3_se0_2uart: qcom,qup_uart@0x880000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x880000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S0_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_2uart_active>;

		pinctrl-1 = <&qupv3_se0_2uart_sleep>;

		interrupts = <GIC_SPI 601 0>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* I2C */

	qupv3_se1_i2c: i2c@884000 {

		compatible = "qcom,i2c-geni";

		reg = <0x884000 0x4000>;

		interrupts = <GIC_SPI 602 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S1_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_i2c_active>;

		pinctrl-1 = <&qupv3_se1_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se2_i2c: i2c@888000 {

		compatible = "qcom,i2c-geni";

		reg = <0x888000 0x4000>;

		interrupts = <GIC_SPI 603 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_i2c_active>;

		pinctrl-1 = <&qupv3_se2_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	qupv3_se3_i2c: i2c@88c000 {

		compatible = "qcom,i2c-geni";

		reg = <0x88c000 0x4000>;

		interrupts = <GIC_SPI 604 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S3_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se3_i2c_active>;

		pinctrl-1 = <&qupv3_se3_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se2_spi: spi@888000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x888000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP0_S2_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se2_spi_active>;

		pinctrl-1 = <&qupv3_se2_spi_sleep>;

		interrupts = <GIC_SPI 603 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

	};



	/* QUPv3 North instances */

	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0xac0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x363 0x0>;

		};

	};



	/* I2C */

	qupv3_se4_i2c: i2c@a80000 {

		compatible = "qcom,i2c-geni";

		reg = <0xa80000 0x4000>;

		interrupts = <GIC_SPI 353 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_i2c_active>;

		pinctrl-1 = <&qupv3_se4_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	qupv3_se5_i2c: i2c@a84000 {

		compatible = "qcom,i2c-geni";

		reg = <0xa84000 0x4000>;

		interrupts = <GIC_SPI 354 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S1_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_i2c_active>;

		pinctrl-1 = <&qupv3_se5_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	qupv3_se6_i2c: i2c@a88000 {

		compatible = "qcom,i2c-geni";

		reg = <0xa88000 0x4000>;

		interrupts = <GIC_SPI 355 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_i2c_active>;

		pinctrl-1 = <&qupv3_se6_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	qupv3_se7_i2c: i2c@a8c000 {

		compatible = "qcom,i2c-geni";

		reg = <0xa8c000 0x4000>;

		interrupts = <GIC_SPI 356 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se7_i2c_active>;

		pinctrl-1 = <&qupv3_se7_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se4_spi: spi@a80000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa80000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S0_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se4_spi_active>;

		pinctrl-1 = <&qupv3_se4_spi_sleep>;

		interrupts = <GIC_SPI 353 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	qupv3_se6_spi: spi@a88000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa88000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S2_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se6_spi_active>;

		pinctrl-1 = <&qupv3_se6_spi_sleep>;

		interrupts = <GIC_SPI 355 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	qupv3_se7_spi: spi@a8c000 {

		compatible = "qcom,spi-geni";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0xa8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se7_spi_active>;

		pinctrl-1 = <&qupv3_se7_spi_sleep>;

		interrupts = <GIC_SPI 356 0>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_1>;

		status = "disabled";

	};



	/*

	 * HS UART instances. HS UART usecases can be supported on these

	 * instances only.

	 */

	qupv3_se7_4uart: qcom,qup_uart@0xa8c000 {

		compatible = "qcom,msm-geni-serial-hs";

		reg = <0xa8c000 0x4000>;

		reg-names = "se_phys";

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt GCC_QUPV3_WRAP1_S3_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_M_AHB_CLK>,

			<&clock_virt GCC_QUPV3_WRAP_1_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,

						<&qupv3_se7_tx>;

		pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,

						<&qupv3_se7_tx>;

		interrupts = <GIC_SPI 356 0>;

		status = "disabled";

		qcom,wakeup-byte = <0xFD>;

		qcom,wrapper-core = <&qupv3_1>;

	};



	/* QUPv3 SSC Instances */

	qupv3_2: qcom,qupv3_2_geni_se@626c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x626c0000 0x6000>;

		qcom,bus-mas-id = <MSM_BUS_MASTER_LPASS_ANOC>;

		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;

		qcom,iommu-s1-bypass;



		iommu_qupv3_2_geni_se_cb: qcom,iommu_qupv3_2_geni_se_cb {

			compatible = "qcom,qupv3-geni-se-cb";

			iommus = <&apps_smmu 0x1783 0x0>;

		};

	};



	/* I2C */

	qupv3_se8_i2c: i2c@62680000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62680000 0x4000>;

		interrupts = <GIC_SPI 442 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE0_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se8_i2c_active>;

		pinctrl-1 = <&qupv3_se8_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se9_i2c: i2c@62684000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62684000 0x4000>;

		interrupts = <GIC_SPI 443 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_i2c_active>;

		pinctrl-1 = <&qupv3_se9_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se10_i2c: i2c@62688000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62688000 0x4000>;

		interrupts = <GIC_SPI 444 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_i2c_active>;

		pinctrl-1 = <&qupv3_se10_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se11_i2c: i2c@6268c000 {

		compatible = "qcom,i2c-geni";

		reg = <0x6268c000 0x4000>;

		interrupts = <GIC_SPI 445 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE3_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se11_i2c_active>;

		pinctrl-1 = <&qupv3_se11_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se12_i2c: i2c@62690000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62690000 0x4000>;

		interrupts = <GIC_SPI 446 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE4_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se12_i2c_active>;

		pinctrl-1 = <&qupv3_se12_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se13_i2c: i2c@62694000 {

		compatible = "qcom,i2c-geni";

		reg = <0x62694000 0x4000>;

		interrupts = <GIC_SPI 447 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE5_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_i2c_active>;

		pinctrl-1 = <&qupv3_se13_i2c_sleep>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	/* SPI */

	qupv3_se9_spi: spi@62684000 {

		compatible = "qcom,spi-geni";

		reg = <0x62684000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 443 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE1_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se9_spi_active>;

		pinctrl-1 = <&qupv3_se9_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};



	qupv3_se10_spi: spi@62688000 {

		compatible = "qcom,spi-geni";

		reg = <0x62688000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 444 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_virt_scc SCC_QUPV3_SE2_CLK>,

			<&clock_virt_scc SCC_QUPV3_M_HCLK_CLK>,

			<&clock_virt_scc SCC_QUPV3_S_HCLK_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_spi_active>;

		pinctrl-1 = <&qupv3_se10_spi_sleep>;

		spi-max-frequency = <50000000>;

		qcom,wrapper-core = <&qupv3_2>;

		status = "disabled";

	};

};

arch/arm64/boot/dts/qcom/sa6155p-vm-usb.dtsi

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/* Copyright (c) 2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/clock/qcom,gcc-sm6150.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/msm/msm-bus-ids.h>



&soc {

	/* Primary USB port related controller */

	usb0: ssusb@a600000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0xa600000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0x140 0x0>;

		qcom,smmu-s1-bypass;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		interrupts = <0 489 0>, <0 130 0>, <0 486 0>, <0 488 0>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"ss_phy_irq", "dm_hs_phy_irq";

		qcom,use-pdc-interrupts;



		USB3_GDSC-supply = <&usb30_prim_gdsc>;

		dpdm-supply = <&qusb_phy0>;

		clocks = <&clock_virt  GCC_USB30_PRIM_MASTER_CLK>,

			<&clock_virt GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

			<&clock_virt GCC_AGGRE_USB3_PRIM_AXI_CLK>,

			<&clock_virt GCC_USB3_PRIM_CLKREF_CLK>,

			<&clock_virt GCC_USB30_PRIM_SLEEP_CLK>,

			<&clock_virt GCC_USB30_PRIM_MOCK_UTMI_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

				"xo", "sleep_clk", "utmi_clk";



		resets = <&clock_virt GCC_USB30_PRIM_BCR>;

		reset-names = "core_reset";



		qcom,core-clk-rate = <200000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,num-gsi-evt-buffs = <0x3>;

		qcom,gsi-reg-offset =

			<0x0fc /* GSI_GENERAL_CFG */

			 0x110 /* GSI_DBL_ADDR_L */

			 0x120 /* GSI_DBL_ADDR_H */

			 0x130 /* GSI_RING_BASE_ADDR_L */

			 0x144 /* GSI_RING_BASE_ADDR_H */

			 0x1a4>; /* GSI_IF_STS */

		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;

		qcom,pm-qos-latency = <61>;

		status = "disabled";

		dwc3@a600000 {

			compatible = "snps,dwc3";

			reg = <0xa600000 0xcd00>;

			interrupts = <0 133 0>;

			usb-phy = <&qusb_phy0>, <&usb_nop_phy>;

			tx-fifo-resize;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,dis_u2_susphy_quirk;

			snps,dis_enblslpm_quirk;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

			snps,usb3_lpm_capable;

			usb-core-id = <0>;

			maximum-speed = "high-speed";

			dr_mode = "otg";

		};



		usbbam: qcom,usbbam@a704000 {

			compatible = "qcom,usb-bam-msm";

			reg = <0xa704000 0x17000>;

			interrupts = <0 132 0>;



			qcom,usb-bam-fifo-baseaddr = <0x146a6000>;

			qcom,usb-bam-num-pipes = <4>;

			qcom,disable-clk-gating;

			qcom,usb-bam-override-threshold = <0x4001>;

			qcom,usb-bam-max-mbps-highspeed = <400>;

			qcom,usb-bam-max-mbps-superspeed = <3600>;

			qcom,reset-bam-on-connect;

			status = "disabled";

			qcom,pipe0 {

				label = "ssusb-qdss-in-0";

				qcom,usb-bam-mem-type = <2>;

				qcom,dir = <1>;

				qcom,pipe-num = <0>;

				qcom,peer-bam = <0>;

				qcom,peer-bam-physical-address = <0x6064000>;

				qcom,src-bam-pipe-index = <0>;

				qcom,dst-bam-pipe-index = <0>;

				qcom,data-fifo-offset = <0x0>;

				qcom,data-fifo-size = <0x1800>;

				qcom,descriptor-fifo-offset = <0x1800>;

				qcom,descriptor-fifo-size = <0x800>;

			};

		};

	};



	/* Primary USB port related High Speed PHY */

	qusb_phy0: qusb@88e2000 {

		compatible = "qcom,qusb2phy";

		reg = <0x88e2000 0x180>,

			<0x01fcb250 0x4>,

			<0x007801f8 0x4>,

			<0x01fcb3e4 0x4>;

		reg-names = "qusb_phy_base",

			"tcsr_clamp_dig_n_1p8",

			"tune2_efuse_addr",

			"tcsr_conn_box_spare_0";



		vdd-supply = <&pm6150_l4>;

		vdda18-supply = <&pm6150_l11>;

		vdda33-supply = <&pm6150_l17>;

		qcom,vdd-voltage-level = <0 925000 975000>;

		qcom,tune2-efuse-bit-pos = <25>;

		qcom,tune2-efuse-num-bits = <4>;

		qcom,qusb-phy-init-seq = <0xc8 0x80

					0xb3 0x84

					0x83 0x88

					0xc0 0x8c

					0x30 0x08

					0x79 0x0c

					0x21 0x10

					0x14 0x9c

					0x9f 0x1c

					0x00 0x18>;

		phy_type = "utmi";

		qcom,phy-clk-scheme = "cml";

		qcom,major-rev = <1>;



		/* USB2PHY gets clock directly from CXO pad

		 * connected to differential pin cxo_core_in_1p8_vdda.

		 */

		clocks = <&clock_gcc RPMH_CXO_CLK>,

			<&clock_virt GCC_AHB2PHY_WEST_CLK>;

		clock-names =  "ref_clk_src", "cfg_ahb_clk";



		resets = <&clock_virt GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		status = "disabled";

	};



	/* Primary USB port related QMP USB PHY */

	usb_qmp_phy: ssphy@88e6000 {

		compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";

		reg = <0x88e6000 0x1000>,

			<0x01fcb244 0x4>;

		reg-names = "qmp_phy_base",

			"vls_clamp_reg";



		vdd-supply = <&pm6150_l4>;

		core-supply = <&pm6150_l11>;

		qcom,vdd-voltage-level = <0 925000 975000>;

		qcom,core-voltage-level = <0 1800000 1800000>;

		qcom,qmp-phy-init-seq =

			/* <reg_offset, value, delay> */

				<0xac  0x14 0x00

				 0x34  0x08 0x00

				 0x174 0x30 0x00

				 0x3c  0x06 0x00

				 0xb4  0x00 0x00

				 0xb8  0x08 0x00

				 0x70  0x0f 0x00

				 0x19c 0x01 0x00

				 0x178 0x00 0x00

				 0xd0  0x82 0x00

				 0xdc  0x55 0x00

				 0xe0  0x55 0x00

				 0xe4  0x03 0x00

				 0x78  0x0b 0x00

				 0x84  0x16 0x00

				 0x90  0x28 0x00

				 0x108 0x80 0x00

				 0x10c 0x00 0x00

				 0x184 0x0a 0x00

				 0x4c  0x15 0x00

				 0x50  0x34 0x00

				 0x54  0x00 0x00

				 0xc8  0x00 0x00

				 0x18c 0x00 0x00

				 0xcc  0x00 0x00

				 0x128 0x00 0x00

				 0x0c  0x0a 0x00

				 0x10  0x01 0x00

				 0x1c  0x31 0x00

				 0x20  0x01 0x00

				 0x14  0x00 0x00

				 0x18  0x00 0x00

				 0x24  0xde 0x00

				 0x28  0x07 0x00

				 0x48  0x0f 0x00

				 0x194 0x06 0x00

				 0x100 0x80 0x00

				 0xa8  0x01 0x00

				 0x430 0x0b 0x00

				 0x830 0x0b 0x00

				 0x444 0x00 0x00

				 0x844 0x00 0x00

				 0x43c 0x00 0x00

				 0x83c 0x00 0x00

				 0x440 0x00 0x00

				 0x840 0x00 0x00

				 0x408 0x0a 0x00

				 0x808 0x0a 0x00

				 0x414 0x06 0x00

				 0x814 0x06 0x00

				 0x434 0x75 0x00

				 0x834 0x75 0x00

				 0x4d4 0x02 0x00

				 0x8d4 0x02 0x00

				 0x4d8 0x4e 0x00

				 0x8d8 0x4e 0x00

				 0x4dc 0x18 0x00

				 0x8dc 0x18 0x00

				 0x4f8 0x77 0x00

				 0x8f8 0x77 0x00

				 0x4fc 0x80 0x00

				 0x8fc 0x80 0x00

				 0x4c0 0x0a 0x00

				 0x8c0 0x0a 0x00

				 0x504 0x03 0x00

				 0x904 0x03 0x00

				 0x50c 0x16 0x00

				 0x90c 0x16 0x00

				 0x500 0x00 0x00

				 0x900 0x00 0x00

				 0x564 0x00 0x00

				 0x964 0x00 0x00

				 0x260 0x10 0x00

				 0x660 0x10 0x00

				 0x2a4 0x12 0x00

				 0x6a4 0x12 0x00

				 0x28c 0xc6 0x00

				 0x68c 0xc6 0x00

				 0x244 0x00 0x00

				 0x644 0x00 0x00

				 0x248 0x00 0x00

				 0x648 0x00 0x00

				 0xc0c 0x9f 0x00

				 0xc24 0x17 0x00

				 0xc28 0x0f 0x00

				 0xcc8 0x83 0x00

				 0xcc4 0x02 0x00

				 0xccc 0x09 0x00

				 0xcd0 0xa2 0x00

				 0xcd4 0x85 0x00

				 0xc80 0xd1 0x00

				 0xc84 0x1f 0x00

				 0xc88 0x47 0x00

				 0xcb8 0x75 0x00

				 0xcbc 0x13 0x00

				 0xcb0 0x86 0x00

				 0xca0 0x04 0x00

				 0xc8c 0x44 0x00

				 0xc70 0xe7 0x00

				 0xc74 0x03 0x00

				 0xc78 0x40 0x00

				 0xc7c 0x00 0x00

				 0xdd8 0x88 0x00

				 0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

				<0xd74 /* USB3_PHY_PCS_STATUS */

				 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */

				 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */

				 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */

				 0xc00 /* USB3_PHY_SW_RESET */

				 0xc08 /* USB3_PHY_START */

				 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */



		clocks = <&clock_virt GCC_USB3_PRIM_PHY_AUX_CLK>,

			<&clock_virt GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&clock_gcc RPMH_CXO_CLK>,

			<&clock_virt GCC_USB3_PRIM_CLKREF_CLK>,

			<&clock_virt GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

			<&clock_virt GCC_AHB2PHY_WEST_CLK>;



		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",

				"ref_clk", "com_aux_clk", "cfg_ahb_clk";



		resets = <&clock_virt GCC_USB3_PHY_PRIM_SP0_BCR>,

			<&clock_virt GCC_USB3PHY_PHY_PRIM_SP0_BCR>;

		reset-names = "phy_reset", "phy_phy_reset";

		status = "disabled";

	};



	usb_audio_qmi_dev {

		compatible = "qcom,usb-audio-qmi-dev";

		iommus = <&apps_smmu 0x172f 0x0>;

		qcom,usb-audio-stream-id = <0xf>;

		qcom,usb-audio-intr-num = <2>;

		status = "disabled";

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};



	/* Secondary USB port related controller */

	usb1: hsusb@a800000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0xa800000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0xE0 0x0>;

		qcom,smmu-s1-bypass;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		interrupts = <0 491 0>, <0 663 0>, <0 490 0>;

		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",

				"dm_hs_phy_irq";

		qcom,use-pdc-interrupts;



		USB3_GDSC-supply = <&usb20_sec_gdsc>;

		clocks = <&clock_virt  GCC_USB20_SEC_MASTER_CLK>,

			<&clock_virt GCC_CFG_NOC_USB2_SEC_AXI_CLK>,

			<&clock_virt GCC_AGGRE_USB2_SEC_AXI_CLK>,

			<&clock_virt GCC_USB3_SEC_CLKREF_CLK>,

			<&clock_virt GCC_USB20_SEC_SLEEP_CLK>,

			<&clock_virt GCC_USB20_SEC_MOCK_UTMI_CLK>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

				"xo", "sleep_clk", "utmi_clk";



		resets = <&clock_virt GCC_USB20_SEC_BCR>;

		reset-names = "core_reset";



		qcom,core-clk-rate = <120000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;

		qcom,charging-disabled;



		status = "disabled";



		dwc3@a800000 {

			compatible = "snps,dwc3";

			reg = <0xa800000 0xcd00>;

			interrupts = <0 664 0>;

			usb-phy = <&qusb_phy1>, <&usb_nop_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,dis_u2_susphy_quirk;

			snps,dis_enblslpm_quirk;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

			snps,usb3_lpm_capable;

			usb-core-id = <1>;

			maximum-speed = "high-speed";

			dr_mode = "otg";

		};

	};



	/* Secondary USB port related High Speed PHY */

	qusb_phy1: qusb@88e3000 {

		compatible = "qcom,qusb2phy";

		reg = <0x88e3000 0x180>,

			<0x01fcb3e4 0x4>;

		reg-names = "qusb_phy_base",

			"tcsr_conn_box_spare_0";



		vdd-supply = <&pm6150_l4>;

		vdda18-supply = <&pm6150_l11>;

		vdda33-supply = <&pm6150_l17>;

		qcom,vdd-voltage-level = <0 925000 975000>;

		qcom,qusb-phy-init-seq = <0xc8 0x80

					0xb3 0x84

					0x83 0x88

					0xc0 0x8c

					0x30 0x08

					0x79 0x0c

					0x21 0x10

					0x14 0x9c

					0x9f 0x1c

					0x00 0x18>;

		phy_type = "utmi";

		qcom,phy-clk-scheme = "cml";

		qcom,major-rev = <1>;

		qcom,hold-reset;



		/* USB2PHY gets clock directly from CXO pad

		 * connected to differential pin cxo_core_in_1p8_vdda.

		 */

		clocks = <&clock_gcc RPMH_CXO_CLK>,

			<&clock_virt GCC_AHB2PHY_WEST_CLK>;

		clock-names =  "ref_clk_src", "cfg_ahb_clk";



		resets = <&clock_virt GCC_QUSB2PHY_SEC_BCR>;

		reset-names = "phy_reset";

		status = "disabled";

	};



};

arch/arm64/boot/dts/qcom/sa6155p-vm.dts

+16 −0
Original line number Diff line number Diff line
@@ -21,3 +21,19 @@ 
	qcom,pmic-name = "PM6150";

	qcom,board-id = <0 0>;

};



&slpi_tlmm {

	status = "ok";

};



&apps_smmu {

	status = "ok";

};



&usb0 {

	status = "ok";

};



&qusb_phy0 {

	status = "ok";

};

arch/arm64/boot/dts/qcom/sa6155p-vm.dtsi

+143 −0

File changed.

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