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Commit 0c420cea authored by Veera Vegivada's avatar Veera Vegivada
Browse files

clk: qcom: sm6150: Add support for enabling the critical clocks



Add pm_ops to re-enable the critical clocks in the restore path.

Change-Id: I302085960194a544dcf492680a96bf3012999e2d
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent 4042fa04
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+29 −0
Original line number Diff line number Diff line
@@ -3597,6 +3597,24 @@ static struct clk_dfs gcc_dfs_clocks[] = {
	{ &gcc_qupv3_wrap1_s5_clk_src, DFS_ENABLE_RCG },
};

static struct clk_regmap *gcc_sm6150_critical_clocks[] = {
	&gcc_camera_ahb_clk.clkr,
	&gcc_camera_xo_clk.clkr,
	&gcc_cpuss_ahb_clk.clkr,
	&gcc_cpuss_gnoc_clk.clkr,
	&gcc_disp_ahb_clk.clkr,
	&gcc_disp_xo_clk.clkr,
	&gcc_gpu_cfg_ahb_clk.clkr,
	&gcc_sys_noc_cpuss_ahb_clk.clkr,
	&gcc_video_ahb_clk.clkr,
	&gcc_video_xo_clk.clkr
};

static const struct qcom_cc_critical_desc gcc_sm6150_critical_desc = {
	.clks = gcc_sm6150_critical_clocks,
	.num_clks = ARRAY_SIZE(gcc_sm6150_critical_clocks),
};

static const struct qcom_cc_dfs_desc gcc_sm6150_dfs_desc = {
	.clks = gcc_dfs_clocks,
	.num_clks = ARRAY_SIZE(gcc_dfs_clocks),
@@ -3627,12 +3645,23 @@ static const struct of_device_id gcc_sm6150_match_table[] = {
};
MODULE_DEVICE_TABLE(of, gcc_sm6150_match_table);

static int gcc_sa6150_resume(struct device *dev)
{
	return qcom_cc_enable_critical_clks(&gcc_sm6150_critical_desc);
}

static const struct dev_pm_ops gcc_sa6150_pm_ops = {
	.restore_early = gcc_sa6150_resume,
};

static void gcc_sm6150_fixup_sa6155(struct platform_device *pdev)
{
	vdd_cx.num_levels = VDD_NUM_SA6155;
	vdd_cx.cur_level = VDD_NUM_SA6155;
	vdd_cx_ao.num_levels = VDD_NUM_SA6155;
	vdd_cx_ao.cur_level = VDD_NUM_SA6155;

	pdev->dev.driver->pm =  &gcc_sa6150_pm_ops;
}

static int gcc_sm6150_probe(struct platform_device *pdev)
+10 −1
Original line number Diff line number Diff line
@@ -508,6 +508,15 @@ static const struct qcom_cc_desc gpu_cc_sm6150_desc = {
	.num_hwclks = ARRAY_SIZE(gpu_cc_sm6150_hws),
};

static struct clk_regmap *gpu_cc_sm6150_critical_clocks[] = {
	&gpu_cc_ahb_clk.clkr,
};

static const struct qcom_cc_critical_desc gpu_cc_sm6150_critical_desc = {
	.clks = gpu_cc_sm6150_critical_clocks,
	.num_clks = ARRAY_SIZE(gpu_cc_sm6150_critical_clocks),
};

static const struct of_device_id gpu_cc_sm6150_match_table[] = {
	{ .compatible = "qcom,gpucc-sm6150" },
	{ .compatible = "qcom,gpucc-sa6155" },
@@ -541,7 +550,7 @@ static int gpu_cc_sm6150_resume(struct device *dev)

	gpu_cc_sm6150_configure(regmap);

	return 0;
	return qcom_cc_enable_critical_clks(&gpu_cc_sm6150_critical_desc);
}

static const struct dev_pm_ops gpu_cc_sm6150_pm_ops = {
+21 −0
Original line number Diff line number Diff line
@@ -326,6 +326,15 @@ static const struct qcom_cc_desc video_cc_sm6150_desc = {
	.num_clks = ARRAY_SIZE(video_cc_sm6150_clocks),
};

static struct clk_regmap *video_cc_sm6150_critical_clocks[] = {
	&video_cc_xo_clk.clkr,
};

static const struct qcom_cc_critical_desc video_cc_sm6150_critical_desc = {
	.clks = video_cc_sm6150_critical_clocks,
	.num_clks = ARRAY_SIZE(video_cc_sm6150_critical_clocks),
};

static const struct of_device_id video_cc_sm6150_match_table[] = {
	{ .compatible = "qcom,videocc-sm6150" },
	{ .compatible = "qcom,videocc-sa6155" },
@@ -333,10 +342,22 @@ static const struct of_device_id video_cc_sm6150_match_table[] = {
};
MODULE_DEVICE_TABLE(of, video_cc_sm6150_match_table);

static int video_cc_sa6150_resume(struct device *dev)
{
	return qcom_cc_enable_critical_clks(&video_cc_sm6150_critical_desc);
}

static const struct dev_pm_ops video_cc_sa6150_pm_ops = {
	.restore_early = video_cc_sa6150_resume,
};


static void videocc_sm6150_fixup_sa6155(struct platform_device *pdev)
{
	vdd_cx.num_levels = VDD_NUM_SA6155;
	vdd_cx.cur_level = VDD_NUM_SA6155;

	pdev->dev.driver->pm =  &video_cc_sa6150_pm_ops;
}

static int video_cc_sm6150_probe(struct platform_device *pdev)