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Commit 0beb059a authored by Akash Goel's avatar Akash Goel Committed by Daniel Vetter
Browse files

drm/i915/skl: Updated the gen9_enable_rps function 



On SKL, GT frequency is programmed in units of 16.66 MHZ units compared
to 50 MHZ for older platforms. Also the time value specified for Up/Down EI &
Up/Down thresholds are expressed in units of 1.33 us, compared to 1.28
us for older platforms. So updated the gen9_enable_rps function as per that.

v2: Updated to use new macro GT_INTERVAL_FROM_US

v3: Removed the initial setup of certain registers, from gen9_enable_rps,
    which gets overridden later from gen6_set_rps (Damien)

v4: Removed the enabling of rps interrupts, from gen9_enable_rps.
    To be done from intel_gen6_powersave_work only, as done for other
    platforms also.

Signed-off-by: default avatarAkash Goel <akash.goel@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 74ef1173

drivers/gpu/drm/i915/intel_pm.c

+13 −15
Original line number Diff line number Diff line
@@ -4233,23 +4233,21 @@ static void gen9_enable_rps(struct drm_device *dev) 


	gen6_init_rps_frequencies(dev);



	I915_WRITE(GEN6_RPNSWREQ, 0xc800000);

	I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);



	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);

	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);

	I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);

	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);

	I915_WRITE(GEN6_RP_UP_EI, 0x101d0);

	I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);

	/* Program defaults and thresholds for RPS*/

	I915_WRITE(GEN6_RC_VIDEO_FREQ,

		GEN9_FREQUENCY(dev_priv->rps.rp1_freq));



	/* 1 second timeout*/

	I915_WRITE(GEN6_RP_DOWN_TIMEOUT,

		GT_INTERVAL_FROM_US(dev_priv, 1000000));



	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);

	I915_WRITE(GEN6_PMINTRMSK, 0x6);

	I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |

		   GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |

		   GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |

		   GEN6_RP_DOWN_IDLE_AVG);



	gen6_enable_rps_interrupts(dev);

	/* Leaning on the below call to gen6_set_rps to program/setup the

	 * Up/Down EI & threshold registers, as well as the RP_CONTROL,

	 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */

	dev_priv->rps.power = HIGH_POWER; /* force a reset */

	gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);



	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

}