Loading drivers/power/supply/qcom/qpnp-smb5.c +1 −4 Original line number Diff line number Diff line Loading @@ -291,11 +291,7 @@ static int smb5_chg_config_init(struct smb5 *chip) #define MICRO_P1A 100000 #define MICRO_1PA 1000000 #define OTG_DEFAULT_DEGLITCH_TIME_MS 50 #define MIN_WD_BARK_TIME 16 #define DEFAULT_WD_BARK_TIME 64 #define BITE_WDOG_TIMEOUT_8S 0x3 #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BARK_WDOG_TIMEOUT_SHIFT 2 static int smb5_parse_dt(struct smb5 *chip) { struct smb_charger *chg = &chip->chg; Loading Loading @@ -2346,6 +2342,7 @@ static struct smb_irq_info smb5_irqs[] = { [WDOG_BARK_IRQ] = { .name = "wdog-bark", .handler = wdog_bark_irq_handler, .wake = true, }, [AICL_FAIL_IRQ] = { .name = "aicl-fail", Loading drivers/power/supply/qcom/smb5-reg.h +8 −5 Original line number Diff line number Diff line Loading @@ -439,11 +439,6 @@ enum { #define AICL_CMD_REG (MISC_BASE + 0x44) #define RERUN_AICL_BIT BIT(0) #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x43) #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) #define MISC_SMB_EN_CMD_REG (MISC_BASE + 0x48) #define SMB_EN_OVERRIDE_VALUE_BIT BIT(4) #define SMB_EN_OVERRIDE_BIT BIT(3) Loading @@ -456,6 +451,14 @@ enum { #define BARK_WDOG_INT_EN_BIT BIT(6) #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1) #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53) #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BARK_WDOG_TIMEOUT_SHIFT 2 #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) #define BITE_WDOG_TIMEOUT_8S 0x3 #define MIN_WD_BARK_TIME 16 #define AICL_RERUN_TIME_CFG_REG (MISC_BASE + 0x61) #define AICL_RERUN_TIME_12S_VAL 0x01 Loading Loading
drivers/power/supply/qcom/qpnp-smb5.c +1 −4 Original line number Diff line number Diff line Loading @@ -291,11 +291,7 @@ static int smb5_chg_config_init(struct smb5 *chip) #define MICRO_P1A 100000 #define MICRO_1PA 1000000 #define OTG_DEFAULT_DEGLITCH_TIME_MS 50 #define MIN_WD_BARK_TIME 16 #define DEFAULT_WD_BARK_TIME 64 #define BITE_WDOG_TIMEOUT_8S 0x3 #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BARK_WDOG_TIMEOUT_SHIFT 2 static int smb5_parse_dt(struct smb5 *chip) { struct smb_charger *chg = &chip->chg; Loading Loading @@ -2346,6 +2342,7 @@ static struct smb_irq_info smb5_irqs[] = { [WDOG_BARK_IRQ] = { .name = "wdog-bark", .handler = wdog_bark_irq_handler, .wake = true, }, [AICL_FAIL_IRQ] = { .name = "aicl-fail", Loading
drivers/power/supply/qcom/smb5-reg.h +8 −5 Original line number Diff line number Diff line Loading @@ -439,11 +439,6 @@ enum { #define AICL_CMD_REG (MISC_BASE + 0x44) #define RERUN_AICL_BIT BIT(0) #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x43) #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) #define MISC_SMB_EN_CMD_REG (MISC_BASE + 0x48) #define SMB_EN_OVERRIDE_VALUE_BIT BIT(4) #define SMB_EN_OVERRIDE_BIT BIT(3) Loading @@ -456,6 +451,14 @@ enum { #define BARK_WDOG_INT_EN_BIT BIT(6) #define WDOG_TIMER_EN_ON_PLUGIN_BIT BIT(1) #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53) #define BITE_WDOG_DISABLE_CHARGING_CFG_BIT BIT(7) #define BARK_WDOG_TIMEOUT_MASK GENMASK(3, 2) #define BARK_WDOG_TIMEOUT_SHIFT 2 #define BITE_WDOG_TIMEOUT_MASK GENMASK(1, 0) #define BITE_WDOG_TIMEOUT_8S 0x3 #define MIN_WD_BARK_TIME 16 #define AICL_RERUN_TIME_CFG_REG (MISC_BASE + 0x61) #define AICL_RERUN_TIME_12S_VAL 0x01 Loading