Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 09a34aa5 authored by Jie Yang's avatar Jie Yang Committed by Mark Brown
Browse files

ASoC: Intel: Used lock version to update shim registers 



We need hold lock each time updating shirm registers, otherwise,
we may set unexpected values to them when they are set in
different thread at different time sequence.

The notification work will be scheduled in global work queue,
which won't hold this sst->spinlock itself, so here we need
change to use the lock version to update shim registers.

Signed-off-by: default avatarJie Yang <yang.jie@intel.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f81677b4

sound/soc/intel/sst-haswell-ipc.c

+2 −2
Original line number Diff line number Diff line
@@ -651,11 +651,11 @@ static void hsw_notification_work(struct work_struct *work) 
	}



	/* tell DSP that notification has been handled */

	sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,

	sst_dsp_shim_update_bits(hsw->dsp, SST_IPCD,

		SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);



	/* unmask busy interrupt */

	sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);

	sst_dsp_shim_update_bits(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);

}



static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)