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Commit 08d3cd5e authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy Committed by Brian Norris
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mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits 



In case if quotient of controller clock rate to device clock rate does
not fit into 4 bit value, choose the maximum acceptable value 0xF, which
stands for 16 clocks.

Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
parent 641f6342

drivers/mtd/nand/lpc32xx_slc.c

+1 −1
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ 
* slc_tac register definitions

**********************************************************************/

/* Computation of clock cycles on basis of controller and device clock rates */

#define SLCTAC_CLOCKS(c, n, s)	(((1 + (c / n)) & 0xF) << s)

#define SLCTAC_CLOCKS(c, n, s)	(min_t(u32, 1 + (c / n), 0xF) << s)



/* Clock setting for RDY write sample wait time in 2*n clocks */

#define SLCTAC_WDR(n)		(((n) & 0xF) << 28)