Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/st-ssc4' and...

STMicroelectronics STM32 SPI Controller

The STM32 SPI controller is used to communicate with external devices using

the Serial Peripheral Interface. It supports full-duplex, half-duplex and

simplex synchronous serial communication with external devices. It supports

from 4 to 32-bit data size. Although it can be configured as master or slave,

only master is supported by the driver.

Required properties:

- compatible: Must be "st,stm32h7-spi".

- reg: Offset and length of the device's register set.

- interrupts: Must contain the interrupt id.

- clocks: Must contain an entry for spiclk (which feeds the internal clock

	  generator).

- #address-cells:  Number of cells required to define a chip select address.

- #size-cells: Should be zero.

Optional properties:

- resets: Must contain the phandle to the reset controller.

- A pinctrl state named "default" may be defined to set pins in mode of

  operation for SPI transfer.

- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the

  STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt.

- dma-names: DMA request names should include "tx" and "rx" if present.

- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,

  Documentation/devicetree/bindings/spi/spi-bus.txt

Child nodes represent devices on the SPI bus

  See ../spi/spi-bus.txt

Optional properties:

- st,spi-midi-ns: (Master Inter-Data Idleness) minimum time delay in

		  nanoseconds inserted between two consecutive data frames.

Example:

	spi2: spi@40003800 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "st,stm32h7-spi";

		reg = <0x40003800 0x400>;

		interrupts = <36>;

		clocks = <&rcc SPI2_CK>;

		resets = <&rcc 1166>;

		dmas = <&dmamux1 0 39 0x400 0x01>,

		       <&dmamux1 1 40 0x400 0x01>;

		dma-names = "rx", "tx";

		pinctrl-0 = <&spi2_pins_b>;

		pinctrl-names = "default";

		cs-gpios = <&gpioa 11 0>;

		aardvark@0 {

			compatible = "totalphase,aardvark";

			reg = <0>;

			spi-max-frequency = <4000000>;

			st,spi-midi-ns = <4000>;

		};

	};

	help

	  SPI driver for CSR SiRFprimaII SoCs

config SPI_STM32

	tristate "STMicroelectronics STM32 SPI controller"

	depends on ARCH_STM32 || COMPILE_TEST

	help

	  SPI driver for STMicroelectonics STM32 SoCs.

	  STM32 SPI controller supports DMA and PIO modes. When DMA

	  is not available, the driver automatically falls back to

	  PIO mode.

config SPI_ST_SSC4

	tristate "STMicroelectronics SPI SSC-based driver"

	depends on ARCH_STI || COMPILE_TEST

obj-$(CONFIG_SPI_SH_MSIOF)		+= spi-sh-msiof.o

obj-$(CONFIG_SPI_SH_SCI)		+= spi-sh-sci.o

obj-$(CONFIG_SPI_SIRF)		+= spi-sirf.o

obj-$(CONFIG_SPI_STM32) 		+= spi-stm32.o

obj-$(CONFIG_SPI_ST_SSC4)		+= spi-st-ssc4.o

obj-$(CONFIG_SPI_SUN4I)			+= spi-sun4i.o

obj-$(CONFIG_SPI_SUN6I)			+= spi-sun6i.o

static ssize_t

spidev_sync(struct spidev_data *spidev, struct spi_message *message)

{

	DECLARE_COMPLETION_ONSTACK(done);

	int status;

	struct spi_device *spi;

spidev_get_ioc_message(unsigned int cmd, struct spi_ioc_transfer __user *u_ioc,

		unsigned *n_ioc)

{

	struct spi_ioc_transfer	*ioc;

	u32	tmp;

	/* Check type, command number and direction */

		return NULL;

	/* copy into scratch area */

	ioc = kmalloc(tmp, GFP_KERNEL);

	if (!ioc)

		return ERR_PTR(-ENOMEM);

	if (__copy_from_user(ioc, u_ioc, tmp)) {

		kfree(ioc);

		return ERR_PTR(-EFAULT);

	}

	return ioc;

	return memdup_user(u_ioc, tmp);

}

static long