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Commit 082bb85f authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Ulf Hansson
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mmc: sunxi: Fix clock rate passed to sunxi_mmc_clk_set_phase 



sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed
to it. When the internal divider code was reworked in change ("mmc: sunxi:
Support MMC DDR52 transfer mode with new timing mode"), this requirement
was missed, and the module clock rate was passed in instead. This broke 8
bit DDR MMC on old controllers, as the module clock rate is double the
card clock rate, for which we have no valid delay settings.

Fix this by applying the internal divider to the clock rate right after
we configure it in hardware.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 41279f01

drivers/mmc/host/sunxi-mmc.c

+5 −1
Original line number Original line Diff line number Diff line
@@ -821,6 +821,9 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 
	rval |= div - 1;

	rval |= div - 1;

	mmc_writel(host, REG_CLKCR, rval);

	mmc_writel(host, REG_CLKCR, rval);





	/* update card clock rate to account for internal divider */

	rate /= div;



	if (host->use_new_timings) {

	if (host->use_new_timings) {

		/* Don't touch the delay bits */

		/* Don't touch the delay bits */

		rval = mmc_readl(host, REG_SD_NTSR);

		rval = mmc_readl(host, REG_SD_NTSR);
@@ -828,6 +831,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 
		mmc_writel(host, REG_SD_NTSR, rval);

		mmc_writel(host, REG_SD_NTSR, rval);

	}

	}





	/* sunxi_mmc_clk_set_phase expects the actual card clock rate */

	ret = sunxi_mmc_clk_set_phase(host, ios, rate);

	ret = sunxi_mmc_clk_set_phase(host, ios, rate);

	if (ret)

	if (ret)

		return ret;

		return ret;
@@ -849,7 +853,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 
		return ret;

		return ret;





	/* And we just enabled our clock back */

	/* And we just enabled our clock back */

	mmc->actual_clock = rate / div;

	mmc->actual_clock = rate;





	return 0;

	return 0;

}

}