Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 07e796a9 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add inline crypto engine node for atoll"

parents 5ef9de93 1d903d17

arch/arm64/boot/dts/qcom/atoll.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -985,6 +985,51 @@ 
		qcom,rtb-size = <0x100000>;

	};



	ufs_ice: ufsice@1d90000 {

		compatible = "qcom,ice";

		reg = <0x1d90000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk", "bus_clk",

			"iface_clk", "ice_core_clk";

		clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_phy_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<1 757 0 0>,    /* No vote */

			<1 757 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";

	};



	sdcc1_ice: sdcc1ice@7c8000{

		compatible = "qcom,ice";

		reg = <0x7c8000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ice_core_clk_src", "ice_core_clk",

				"bus_clk", "iface_clk";

		clocks = <&clock_gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,

			<&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,

			<&clock_gcc GCC_SDCC1_AHB_CLK>,

			<&clock_gcc GCC_SDCC1_APPS_CLK>;

		qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;

		qcom,msm-bus,name = "sdcc_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<1 608 0 0>,    /* No vote */

			<1 608 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "sdcc";

	};



	wdog: qcom,wdt@17c10000{

		compatible = "qcom,msm-watchdog";

		reg = <0x17c10000 0x1000>;
@@ -2143,6 +2188,7 @@ 
		interrupts = <GIC_SPI 641 IRQ_TYPE_NONE>,

					<GIC_SPI 644 IRQ_TYPE_NONE>;

		interrupt-names = "hc_irq", "pwr_irq";

		sdhc-msm-crypto = <&sdcc1_ice>;



		qcom,bus-width = <8>;

		qcom,large-address-bus;
@@ -2221,6 +2267,7 @@ 
		interrupts = <0 265 0>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs_ice>;



		lanes-per-direction = <1>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */