Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus (07b75260) · Commits · e / devices / android_kernel_xiaomi_nabu

Documentation/devicetree/bindings/clock/microchip,pic32.txt

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		Microchip PIC32 Clock Controller Binding
		----------------------------------------
		Microchip clock controller is consists of few oscillators, PLL, multiplexer
		and few divider modules.

		This binding uses common clock bindings.
		[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

		Required properties:
		- compatible: shall be "microchip,pic32mzda-clk".
		- reg: shall contain base address and length of clock registers.
		- #clock-cells: shall be 1.

		Optional properties:
		- microchip,pic32mzda-sosc: shall be added only if platform has
		secondary oscillator connected.

		Example:
		rootclk: clock-controller@1f801200 {
		compatible = "microchip,pic32mzda-clk";
		reg = <0x1f801200 0x200>;
		#clock-cells = <1>;
		/* optional */
		microchip,pic32mzda-sosc;
		};


		The clock consumer shall specify the desired clock-output of the clock
		controller (as defined in [2]) by specifying output-id in its "clock"
		phandle cell.
		[2] include/dt-bindings/clock/microchip,pic32-clock.h

		For example for UART2:
		uart2: serial@2 {
		compatible = "microchip,pic32mzda-uart";
		reg = <>;
		interrupts = <>;
		clocks = <&rootclk PB2CLK>;
		};

Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt

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		Broadcom BCM6345-style Level 1 interrupt controller

		This block is a first level interrupt controller that is typically connected
		directly to one of the HW INT lines on each CPU.

		Key elements of the hardware design include:

		- 32, 64 or 128 incoming level IRQ lines

		- Most onchip peripherals are wired directly to an L1 input

		- A separate instance of the register set for each CPU, allowing individual
		peripheral IRQs to be routed to any CPU

		- Contains one or more enable/status word pairs per CPU

		- No atomic set/clear operations

		- No polarity/level/edge settings

		- No FIFO or priority encoder logic; software is expected to read all
		2-4 status words to determine which IRQs are pending

		Required properties:

		- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
		- reg: specifies the base physical address and size of the registers;
		the number of supported IRQs is inferred from the size argument
		- interrupt-controller: identifies the node as an interrupt controller
		- #interrupt-cells: specifies the number of cells needed to encode an interrupt
		source, should be 1.
		- interrupt-parent: specifies the phandle to the parent interrupt controller(s)
		this one is cascaded from
		- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
		node; valid values depend on the type of parent interrupt controller

		If multiple reg ranges and interrupt-parent entries are present on an SMP
		system, the driver will allow IRQ SMP affinity to be set up through the
		/proc/irq/ interface. In the simplest possible configuration, only one
		reg range and one interrupt-parent is needed.

		The driver operates in native CPU endian by default, there is no support for
		specifying an alternative endianness.

		Example:

		periph_intc: interrupt-controller@10000000 {
		compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
		reg = <0x10000020 0x20>,
		<0x10000040 0x20>;

		interrupt-controller;
		#interrupt-cells = <1>;

		interrupt-parent = <&cpu_intc>;
		interrupts = <2>, <3>;
		};

Documentation/devicetree/bindings/mips/brcm/soc.txt

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		@@ -4,7 +4,8 @@ Required properties:

		- compatible: "brcm,bcm3384", "brcm,bcm33843"
		"brcm,bcm3384-viper", "brcm,bcm33843-viper"
		"brcm,bcm6328", "brcm,bcm6368",
		"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6368",
		"brcm,bcm63168", "brcm,bcm63268",
		"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
		"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"

Documentation/devicetree/bindings/mips/cavium/ciu3.txt

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		* Central Interrupt Unit v3

		Properties:
		- compatible: "cavium,octeon-7890-ciu3"

		Compatibility with 78XX and 73XX SOCs.

		- interrupt-controller: This is an interrupt controller.

		- reg: The base address of the CIU's register bank.

		- #interrupt-cells: Must be <2>. The first cell is source number.
		The second cell indicates the triggering semantics, and may have a
		value of either 4 for level semantics, or 1 for edge semantics.

		Example:
		interrupt-controller@1010000000000 {
		compatible = "cavium,octeon-7890-ciu3";
		interrupt-controller;
		/* Interrupts are specified by two parts:
		* 1) Source number (20 significant bits)
		* 2) Trigger type: (4 == level, 1 == edge)
		*/
		#address-cells = <0>;
		#interrupt-cells = <2>;
		reg = <0x10100 0x00000000 0x0 0xb0000000>;
		};

Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt

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		* Microchip Universal Asynchronous Receiver Transmitter (UART)

		Required properties:
		- compatible: Should be "microchip,pic32mzda-uart"
		- reg: Should contain registers location and length
		- interrupts: Should contain interrupt
		- clocks: Phandle to the clock.
		See: Documentation/devicetree/bindings/clock/clock-bindings.txt
		- pinctrl-names: A pinctrl state names "default" must be defined.
		- pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
		See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt

		Optional properties:
		- cts-gpios: CTS pin for UART

		Example:
		uart1: serial@1f822000 {
		compatible = "microchip,pic32mzda-uart";
		reg = <0x1f822000 0x50>;
		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>,
		<113 IRQ_TYPE_LEVEL_HIGH>,
		<114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&PBCLK2>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart1
		&pinctrl_uart1_cts
		&pinctrl_uart1_rts>;
		cts-gpios = <&gpio1 15 0>;
		};