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Commit 076fb0c4 authored by Frank Rowand's avatar Frank Rowand Committed by Rob Herring
Browse files

of: update ePAPR references to point to Devicetree Specification 



The Devicetree Specification has superseded the ePAPR as the
base specification for bindings.  Update files in Documentation
to reference the new document.

First reference to ePAPR in Documentation/devicetree/bindings/arm/cci.txt
is generic, remove it.

Some files are not updated because there is no hypervisor chapter
in the Devicetree Specification:
   Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
   Documenation/virtual/kvm/api.txt
   Documenation/virtual/kvm/ppc-pv.txt

Signed-off-by: default avatarFrank Rowand <frank.rowand@sony.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 7782b144

Documentation/devicetree/bindings/arm/cci.txt

+4 −11
Original line number Diff line number Diff line
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register 
space and multiple sets of interface control registers, one per slave

interface.



Bindings for the CCI node follow the ePAPR standard, available from:



www.power.org/documentation/epapr-version-1-1/



with the addition of the bindings described in this document which are

specific to ARM.



* CCI interconnect node



	Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM. 
			    as a tuple of cells, containing child address,

			    parent address and the size of the region in the

			    child address space.

		Definition: A standard property. Follow rules in the ePAPR for

			    hierarchical bus addressing. CCI interfaces

			    addresses refer to the parent node addressing

			    scheme to declare their register bases.

		Definition: A standard property. Follow rules in the Devicetree

			    Specification for hierarchical bus addressing. CCI

			    interfaces addresses refer to the parent node

			    addressing scheme to declare their register bases.



	CCI interconnect node can define the following child nodes:

Documentation/devicetree/bindings/arm/cpus.txt

+7 −6
Original line number Diff line number Diff line
@@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a system through 
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")

defining properties for every cpu.



Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:

Bindings for CPU nodes follow the Devicetree Specification, available from:



https://www.power.org/documentation/epapr-version-1-1/

https://www.devicetree.org/specifications/



with updates for 32-bit and 64-bit ARM systems provided in this document.
@@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in this document. 
Convention used in this document

================================



This document follows the conventions described in the ePAPR v1.1, with

the addition:

This document follows the conventions described in the Devicetree

Specification, with the addition:



- square brackets define bitfields, eg reg[7:0] value of the bitfield in

  the reg property contained in bits 7 down to 0
@@ -26,8 +26,9 @@ the addition: 
cpus and cpu node bindings definition

=====================================



The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu

nodes to be present and contain the properties described below.

The ARM architecture, in accordance with the Devicetree Specification,

requires the cpus and cpu nodes to be present and contain the properties

described below.



- cpus node

Documentation/devicetree/bindings/arm/idle-states.txt

+2 −2
Original line number Diff line number Diff line
@@ -695,5 +695,5 @@ cpus { 
[4] ARM Architecture Reference Manuals

    http://infocenter.arm.com/help/index.jsp



[5] ePAPR standard

    https://www.power.org/documentation/epapr-version-1-1/
 
[5] Devicetree Specification

    https://www.devicetree.org/specifications/

Documentation/devicetree/bindings/arm/l2c2x0.txt

+2 −2
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ 
PL310 and variants) based level 2 cache controller. All these various implementations

of the L2 cache controller have compatible programming models (Note 1).

Some of the properties that are just prefixed "cache-*" are taken from section

3.7.3 of the ePAPR v1.1 specification which can be found at:

https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

3.7.3 of the Devicetree Specification which can be found at:

https://www.devicetree.org/specifications/



The ARM L2 cache representation in the device tree should be done as follows:

Documentation/devicetree/bindings/arm/topology.txt

+2 −2
Original line number Diff line number Diff line
@@ -29,9 +29,9 @@ corresponding to the system hierarchy; syntactically they are defined as device 
tree nodes.



The remainder of this document provides the topology bindings for ARM, based

on the ePAPR standard, available from:

on the Devicetree Specification, available from:



http://www.power.org/documentation/epapr-version-1-1/

https://www.devicetree.org/specifications/



If not stated otherwise, whenever a reference to a cpu node phandle is made its

value must point to a cpu node compliant with the cpu node bindings as