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Commit 0766e2ef authored by Zhenyu Wang's avatar Zhenyu Wang
Browse files

Merge tag 'drm-intel-next-2018-06-06' into gvt-next 



Backmerge for recent request->hw_context change and
new vGPU huge page capability definition.

Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parents 9a512e23 14c3f842

drivers/gpu/drm/i915/gvt/aperture_gm.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -61,7 +61,7 @@ static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm) 
	}

	}





	mutex_lock(&dev_priv->drm.struct_mutex);

	mutex_lock(&dev_priv->drm.struct_mutex);

	ret = i915_gem_gtt_insert(&dev_priv->ggtt.base, node,

	ret = i915_gem_gtt_insert(&dev_priv->ggtt.vm, node,

				  size, I915_GTT_PAGE_SIZE,

				  size, I915_GTT_PAGE_SIZE,

				  I915_COLOR_UNEVICTABLE,

				  I915_COLOR_UNEVICTABLE,

				  start, end, flags);

				  start, end, flags);

drivers/gpu/drm/i915/gvt/display.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -273,8 +273,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
	for_each_pipe(dev_priv, pipe) {

	for_each_pipe(dev_priv, pipe) {

		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;

		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;

		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~CURSOR_MODE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= CURSOR_MODE_DISABLE;

		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;

	}

	}





	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;

	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;

drivers/gpu/drm/i915/gvt/fb_decoder.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -301,16 +301,16 @@ static int cursor_mode_to_drm(int mode) 
	int cursor_pixel_formats_index = 4;

	int cursor_pixel_formats_index = 4;





	switch (mode) {

	switch (mode) {

	case CURSOR_MODE_128_ARGB_AX:

	case MCURSOR_MODE_128_ARGB_AX:

		cursor_pixel_formats_index = 0;

		cursor_pixel_formats_index = 0;

		break;

		break;

	case CURSOR_MODE_256_ARGB_AX:

	case MCURSOR_MODE_256_ARGB_AX:

		cursor_pixel_formats_index = 1;

		cursor_pixel_formats_index = 1;

		break;

		break;

	case CURSOR_MODE_64_ARGB_AX:

	case MCURSOR_MODE_64_ARGB_AX:

		cursor_pixel_formats_index = 2;

		cursor_pixel_formats_index = 2;

		break;

		break;

	case CURSOR_MODE_64_32B_AX:

	case MCURSOR_MODE_64_32B_AX:

		cursor_pixel_formats_index = 3;

		cursor_pixel_formats_index = 3;

		break;

		break;
@@ -343,8 +343,8 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 
		return -ENODEV;

		return -ENODEV;





	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));

	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));

	mode = val & CURSOR_MODE;

	mode = val & MCURSOR_MODE;

	plane->enabled = (mode != CURSOR_MODE_DISABLE);

	plane->enabled = (mode != MCURSOR_MODE_DISABLE);

	if (!plane->enabled)

	if (!plane->enabled)

		return -ENODEV;

		return -ENODEV;

drivers/gpu/drm/i915/gvt/gvt.h

+2 −2
Original line number Original line Diff line number Diff line
@@ -377,9 +377,9 @@ int intel_gvt_load_firmware(struct intel_gvt *gvt); 
#define gvt_aperture_sz(gvt)	  (gvt->dev_priv->ggtt.mappable_end)

#define gvt_aperture_sz(gvt)	  (gvt->dev_priv->ggtt.mappable_end)

#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)

#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)





#define gvt_ggtt_gm_sz(gvt)	  (gvt->dev_priv->ggtt.base.total)

#define gvt_ggtt_gm_sz(gvt)	  (gvt->dev_priv->ggtt.vm.total)

#define gvt_ggtt_sz(gvt) \

#define gvt_ggtt_sz(gvt) \

	((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)

	((gvt->dev_priv->ggtt.vm.total >> PAGE_SHIFT) << 3)

#define gvt_hidden_sz(gvt)	  (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))

#define gvt_hidden_sz(gvt)	  (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))





#define gvt_aperture_gmadr_base(gvt) (0)

#define gvt_aperture_gmadr_base(gvt) (0)

drivers/gpu/drm/i915/gvt/mmio_context.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -446,9 +446,9 @@ static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 




#define CTX_CONTEXT_CONTROL_VAL	0x03

#define CTX_CONTEXT_CONTROL_VAL	0x03





bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id)

bool is_inhibit_context(struct intel_context *ce)

{

{

	u32 *reg_state = ctx->__engine[ring_id].lrc_reg_state;

	const u32 *reg_state = ce->lrc_reg_state;

	u32 inhibit_mask =

	u32 inhibit_mask =

		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
@@ -501,7 +501,7 @@ static void switch_mmio(struct intel_vgpu *pre, 
			 * itself.

			 * itself.

			 */

			 */

			if (mmio->in_context &&

			if (mmio->in_context &&

			    !is_inhibit_context(s->shadow_ctx, ring_id))

			    !is_inhibit_context(&s->shadow_ctx->__engine[ring_id]))

				continue;

				continue;





			if (mmio->mask)

			if (mmio->mask)