Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0668b749 authored by Bojun Pan's avatar Bojun Pan Committed by Gerrit - the friendly Code Review server
Browse files

msm: ipa: GSI 2.5 MHI protocol scratch update 



Dependency change for GSI FW #9.0.42.
Change UL Poll Timer Scratch location.

Change-Id: I69412cecc131f74d07f7684e0616b092d7efa685
Signed-off-by: default avatarBojun Pan <bojunp@codeaurora.org>
parent 4f9559a8

drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c

+29 −2
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, 
	struct ipa_mhi_msi_info *msi;

	struct gsi_chan_props ch_props;

	union __packed gsi_channel_scratch ch_scratch;

	union __packed gsi_channel_scratch ch_scratch1;

	struct ipa3_ep_context *ep;

	const struct ipa_gsi_ep_config *ep_cfg;

	struct ipa_ep_cfg_ctrl ep_cfg_ctrl;
@@ -341,8 +342,31 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, 
	} else {

		ch_scratch.mhi.burst_mode_enabled = false;

	}



	if (ipa3_ctx->ipa_hw_type == IPA_HW_v4_5 &&

		ipa3_ctx->platform_type == IPA_PLAT_TYPE_MDM) {

		memset(&ch_scratch1, 0, sizeof(ch_scratch1));

		ch_scratch1.mhi_v2.mhi_host_wp_addr_lo =

			ch_scratch.mhi.mhi_host_wp_addr & 0xFFFFFFFF;

		ch_scratch1.mhi_v2.mhi_host_wp_addr_hi =

			(ch_scratch.mhi.mhi_host_wp_addr & 0x1FF00000000ll)

			>> 32;

		ch_scratch1.mhi_v2.polling_configuration =

			ch_scratch.mhi.polling_configuration;

		ch_scratch1.mhi_v2.assert_bit40 =

			ch_scratch.mhi.assert_bit40;

		ch_scratch1.mhi_v2.burst_mode_enabled =

			ch_scratch.mhi.burst_mode_enabled;

		ch_scratch1.mhi_v2.polling_mode =

			ch_scratch.mhi.polling_mode;

		ch_scratch1.mhi_v2.oob_mod_threshold =

			ch_scratch.mhi.oob_mod_threshold;

		res = gsi_write_channel_scratch(ep->gsi_chan_hdl,

			ch_scratch1);

	} else {

		res = gsi_write_channel_scratch(ep->gsi_chan_hdl,

			ch_scratch);

	}

	if (res) {

		IPA_MHI_ERR("gsi_write_channel_scratch failed %d\n",

			res);
@@ -686,6 +710,9 @@ int ipa3_mhi_resume_channels_internal(enum ipa_client_type client, 
		/* Use GSI update API to not affect non-SWI fields

		 * inside the scratch while in suspend-resume operation

		 */

		/* polling_mode bit remains unchanged for mhi_v2 format,

		 * no update needed for this effort

		 */

		res = gsi_update_mhi_channel_scratch(

			ep->gsi_chan_hdl, ch_scratch.mhi);

		if (res) {

include/linux/msm_gsi.h

+48 −0
Original line number Diff line number Diff line
@@ -595,6 +595,53 @@ struct __packed gsi_mhi_channel_scratch { 
	uint32_t outstanding_threshold:16; /* Not relevant starting GSI 2.5 */

};



/**

 * gsi_mhi_channel_scratch_v2 - MHI protocol SW config area of

 * channel scratch

 *

 * @mhi_host_wp_addr_lo: Valid only when UL/DL Sync En is asserted. Defines

 *                       address in host from which channel write pointer

 *                       should be read in polling mode

 * @mhi_host_wp_addr_hi: Valid only when UL/DL Sync En is asserted. Defines

 *                       address in host from which channel write pointer

 *                       should be read in polling mode

 * @assert_bit40:        1: bit #41 in address should be asserted upon

 *                       IPA_IF.ProcessDescriptor routine (for MHI over PCIe

 *                       transfers)

 *                       0: bit #41 in address should be deasserted upon

 *                       IPA_IF.ProcessDescriptor routine (for non-MHI over

 *                       PCIe transfers)

 * @polling_configuration: Uplink channels: Defines timer to poll on MHI

 *                       context. Range: 1 to 31 milliseconds.

 *                       Downlink channel: Defines transfer ring buffer

 *                       availability threshold to poll on MHI context in

 *                       multiple of 8. Range: 0 to 31, meaning 0 to 258 ring

 *                       elements. E.g., value of 2 indicates 16 ring elements.

 *                       Valid only when Burst Mode Enabled is set to 1

 * @burst_mode_enabled:  0: Burst mode is disabled for this channel

 *                       1: Burst mode is enabled for this channel

 * @polling_mode:        0: the channel is not in polling mode, meaning the

 *                       host should ring DBs.

 *                       1: the channel is in polling mode, meaning the host

 * @oob_mod_threshold:   Defines OOB moderation threshold. Units are in 8

 *                       ring elements.

 *                       should not ring DBs until notified of DB mode/OOB mode

 */

struct __packed gsi_mhi_channel_scratch_v2 {

	uint32_t mhi_host_wp_addr_lo;

	uint32_t mhi_host_wp_addr_hi:9;

	uint32_t polling_configuration:5;

	uint32_t rsvd1:18;

	uint32_t rsvd2:1;

	uint32_t assert_bit40:1;

	uint32_t resvd3:5;

	uint32_t burst_mode_enabled:1;

	uint32_t polling_mode:1;

	uint32_t oob_mod_threshold:5;

	uint32_t resvd4:18; /* Not configured by AP */

	uint32_t resvd5; /* Not configured by AP */

};



/**

 * gsi_xdci_channel_scratch - xDCI protocol SW config area of

 * channel scratch
@@ -844,6 +891,7 @@ union __packed gsi_wdi3_channel_scratch2_reg { 
union __packed gsi_channel_scratch {

	struct __packed gsi_gpi_channel_scratch gpi;

	struct __packed gsi_mhi_channel_scratch mhi;

	struct __packed gsi_mhi_channel_scratch_v2 mhi_v2;

	struct __packed gsi_xdci_channel_scratch xdci;

	struct __packed gsi_wdi_channel_scratch wdi;

	struct __packed gsi_11ad_rx_channel_scratch rx_11ad;