Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 06613e38 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by David S. Miller
Browse files

ravb: fix race updating TCCR 



The TCCR.TSRQn bit may get clearead after TCCR gets read, so that TCCR write
would get skipped. We don't need to check this bit before setting.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 194ac06e

drivers/net/ethernet/renesas/ravb_main.c

+1 −4
Original line number Diff line number Diff line
@@ -1275,7 +1275,6 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 
	u32 dma_addr;

	void *buffer;

	u32 entry;

	u32 tccr;



	spin_lock_irqsave(&priv->lock, flags);

	if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q]) {
@@ -1324,9 +1323,7 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 
	dma_wmb();

	desc->die_dt = DT_FSINGLE;



	tccr = ravb_read(ndev, TCCR);

	if (!(tccr & (TCCR_TSRQ0 << q)))

		ravb_write(ndev, tccr | (TCCR_TSRQ0 << q), TCCR);

	ravb_write(ndev, ravb_read(ndev, TCCR) | (TCCR_TSRQ0 << q), TCCR);



	priv->cur_tx[q]++;

	if (priv->cur_tx[q] - priv->dirty_tx[q] >= priv->num_tx_ring[q] &&