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Commit 04e71d72 authored by Russell King's avatar Russell King
Browse files

Merge branch 'ja-nommu-for-rmk-v2' of git://linux-arm.org/linux-ja into devel-stable 

This includes the following series sent earlier to the list:
 - nommu-fixes
 - R7 Support
 - MPU support

I've left out the ARCH_MULTIPLATFORM/!MMU stuff that Arnd and I were
discussing today until we've reached a conclusion/that's had some more
review.

This is rebased (and re-tested) on your devel-stable branch because
otherwise there were going to be conflicts with Uwe's V7M work now that
you've merged that. I've included the fix for limiting MPU to CPU_V7.
parents fdeb94b5 de829776

arch/arm/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -1414,7 +1414,7 @@ config SMP 
	depends on CPU_V6K || CPU_V7

	depends on GENERIC_CLOCKEVENTS

	depends on HAVE_SMP

	depends on MMU

	depends on MMU || ARM_MPU

	select USE_GENERIC_SMP_HELPERS

	help

	  This enables support for systems with more than one CPU. If you have
@@ -1435,7 +1435,7 @@ config SMP 


config SMP_ON_UP

	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"

	depends on SMP && !XIP_KERNEL

	depends on SMP && !XIP_KERNEL && MMU

	default y

	help

	  SMP kernels contain instructions which fail on non-SMP processors.

arch/arm/Kconfig-nommu

+12 −0
Original line number Diff line number Diff line
@@ -50,3 +50,15 @@ config REMAP_VECTORS_TO_RAM 
	  Otherwise, say 'y' here.  In this case, the kernel will require

	  external support to redirect the hardware exception vectors to

	  the writable versions located at DRAM_BASE.



config ARM_MPU

       bool 'Use the ARM v7 PMSA Compliant MPU'

       depends on CPU_V7

       default y

       help

         Some ARM systems without an MMU have instead a Memory Protection

         Unit (MPU) that defines the type and permissions for regions of

         memory.



         If your CPU has an MPU then you should choose 'y' here unless you

         know that you do not want to use the MPU.

arch/arm/Kconfig.debug

+9 −1
Original line number Diff line number Diff line
@@ -476,6 +476,13 @@ choice 
		  of the tiles using the RS1 memory map, including all new A-class

		  core tiles, FPGA-based SMMs and software models.



	config DEBUG_VEXPRESS_UART0_CRX

		bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"

		depends on ARCH_VEXPRESS && !MMU

		help

		  This option selects UART0 at 0xb0090000. This is appropriate for

		  Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7



	config DEBUG_VT8500_UART0

		bool "Use UART0 on VIA/Wondermedia SoCs"

		depends on ARCH_VT8500
@@ -645,7 +652,8 @@ config DEBUG_LL_INCLUDE 
	default "debug/tegra.S" if DEBUG_TEGRA_UART

	default "debug/ux500.S" if DEBUG_UX500_UART

	default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \

		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1

		DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \

		DEBUG_VEXPRESS_UART0_CRX

	default "debug/vt8500.S" if DEBUG_VT8500_UART0

	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1

	default "mach/debug-macro.S"

arch/arm/include/asm/cp15.h

+5 −0
Original line number Diff line number Diff line
@@ -23,6 +23,11 @@ 
#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/

#define CR_L4	(1 << 15)	/* LDR pc can set T bit			*/

#define CR_DT	(1 << 16)

#ifdef CONFIG_MMU

#define CR_HA	(1 << 17)	/* Hardware management of Access Flag   */

#else

#define CR_BR	(1 << 17)	/* MPU Background region enable (PMSA)  */

#endif

#define CR_IT	(1 << 18)

#define CR_ST	(1 << 19)

#define CR_FI	(1 << 21)	/* Fast interrupt (lower latency mode)	*/

arch/arm/include/asm/cputype.h

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#define CPUID_CACHETYPE	1

#define CPUID_TCM	2

#define CPUID_TLBTYPE	3

#define CPUID_MPUIR	4

#define CPUID_MPIDR	5



#ifdef CONFIG_CPU_V7M