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Commit 0428491c authored by Balbir Singh's avatar Balbir Singh Committed by Michael Ellerman
Browse files

powerpc/mm: Trace tlbie(l) instructions 



Add a trace point for tlbie(l) (Translation Lookaside Buffer Invalidate
Entry (Local)) instructions.

The tlbie instruction has changed over the years, so not all versions
accept the same operands. Use the ISA v3 field operands because they are
the most verbose, we may change them in future.

Example output:

  qemu-system-ppc-5371  [016]  1412.369519: tlbie:
  	tlbie with lpid 0, local 1, rb=67bd8900174c11c1, rs=0, ric=0 prs=0 r=0

Signed-off-by: default avatarBalbir Singh <bsingharora@gmail.com>
[mpe: Add some missing trace_tlbie()s, reword change log]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent d4cfb113

arch/powerpc/include/asm/trace.h

+33 −0
Original line number Diff line number Diff line
@@ -168,6 +168,39 @@ TRACE_EVENT(hash_fault, 
		      __entry->addr, __entry->access, __entry->trap)

);





TRACE_EVENT(tlbie,



	TP_PROTO(unsigned long lpid, unsigned long local, unsigned long rb,

		unsigned long rs, unsigned long ric, unsigned long prs,

		unsigned long r),

	TP_ARGS(lpid, local, rb, rs, ric, prs, r),

	TP_STRUCT__entry(

		__field(unsigned long, lpid)

		__field(unsigned long, local)

		__field(unsigned long, rb)

		__field(unsigned long, rs)

		__field(unsigned long, ric)

		__field(unsigned long, prs)

		__field(unsigned long, r)

		),



	TP_fast_assign(

		__entry->lpid = lpid;

		__entry->local = local;

		__entry->rb = rb;

		__entry->rs = rs;

		__entry->ric = ric;

		__entry->prs = prs;

		__entry->r = r;

		),



	TP_printk("lpid=%ld, local=%ld, rb=0x%lx, rs=0x%lx, ric=0x%lx, "

		"prs=0x%lx, r=0x%lx", __entry->lpid, __entry->local,

		__entry->rb, __entry->rs, __entry->ric, __entry->prs,

		__entry->r)

);



#endif /* _TRACE_POWERPC_H */



#undef TRACE_INCLUDE_PATH

arch/powerpc/kvm/book3s_hv_rm_mmu.c

+9 −2
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <linux/log2.h>



#include <asm/tlbflush.h>

#include <asm/trace.h>

#include <asm/kvm_ppc.h>

#include <asm/kvm_book3s.h>

#include <asm/book3s/64/mmu-hash.h>
@@ -443,17 +444,23 @@ static void do_tlbies(struct kvm *kvm, unsigned long *rbvalues, 
			cpu_relax();

		if (need_sync)

			asm volatile("ptesync" : : : "memory");

		for (i = 0; i < npages; ++i)

		for (i = 0; i < npages; ++i) {

			asm volatile(PPC_TLBIE_5(%0,%1,0,0,0) : :

				     "r" (rbvalues[i]), "r" (kvm->arch.lpid));

			trace_tlbie(kvm->arch.lpid, 0, rbvalues[i],

				kvm->arch.lpid, 0, 0, 0);

		}

		asm volatile("eieio; tlbsync; ptesync" : : : "memory");

		kvm->arch.tlbie_lock = 0;

	} else {

		if (need_sync)

			asm volatile("ptesync" : : : "memory");

		for (i = 0; i < npages; ++i)

		for (i = 0; i < npages; ++i) {

			asm volatile(PPC_TLBIEL(%0,%1,0,0,0) : :

				     "r" (rbvalues[i]), "r" (0));

			trace_tlbie(kvm->arch.lpid, 1, rbvalues[i],

				0, 0, 0, 0);

		}

		asm volatile("ptesync" : : : "memory");

	}

}

arch/powerpc/mm/hash_native_64.c

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <asm/mmu_context.h>

#include <asm/pgtable.h>

#include <asm/tlbflush.h>

#include <asm/trace.h>

#include <asm/tlb.h>

#include <asm/cputable.h>

#include <asm/udbg.h>
@@ -98,6 +99,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) 
			     : "memory");

		break;

	}

	trace_tlbie(0, 0, va, 0, 0, 0, 0);

}



static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
@@ -147,6 +149,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) 
			     : "memory");

		break;

	}

	trace_tlbie(0, 1, va, 0, 0, 0, 0);



}

arch/powerpc/mm/hash_utils_64.c

+2 −0
Original line number Diff line number Diff line
@@ -810,6 +810,8 @@ static void update_hid_for_hash(void) 
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(0), "i"(0), "i"(2), "r"(0) : "memory");

	asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");

	trace_tlbie(0, 0, rb, 0, 2, 0, 0);



	/*

	 * now switch the HID

	 */

arch/powerpc/mm/pgtable-radix.c

+5 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#include <asm/firmware.h>

#include <asm/powernv.h>

#include <asm/sections.h>

#include <asm/trace.h>



#include <trace/events/thp.h>
@@ -198,6 +199,7 @@ static void __init radix_init_pgtable(void) 
	asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :

		     "r" (TLBIEL_INVAL_SET_LPID), "r" (0));

	asm volatile("eieio; tlbsync; ptesync" : : : "memory");

	trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);

}



static void __init radix_init_partition_table(void)
@@ -324,6 +326,9 @@ static void update_hid_for_radix(void) 
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");

	asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");

	trace_tlbie(0, 0, rb, 0, 2, 0, 1);

	trace_tlbie(0, 0, rb, 0, 2, 1, 1);



	/*

	 * now switch the HID

	 */