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Commit 02ee15db authored by David Collins's avatar David Collins
Browse files

clk: qcom: gpucc-kona: remove disable check for several clocks 



Change halt_check to BRANCH_HALT_VOTED for several GPU_CC clocks
which are always enabled when their parent clocks and GDSCs are
enabled.

Change-Id: I4f59b512680e7ffeab5caf511f646b3944c9216b
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent 0945a696

drivers/clk/qcom/gpucc-kona.c

+10 −10
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ static struct clk_branch gpu_cc_ahb_clk = { 


static struct clk_branch gpu_cc_crc_ahb_clk = {

	.halt_reg = 0x107c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x107c,

		.enable_mask = BIT(0),
@@ -149,7 +149,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk = { 


static struct clk_branch gpu_cc_cx_apb_clk = {

	.halt_reg = 0x1088,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1088,

		.enable_mask = BIT(0),
@@ -180,7 +180,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = { 


static struct clk_branch gpu_cc_cx_qdss_at_clk = {

	.halt_reg = 0x1080,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1080,

		.enable_mask = BIT(0),
@@ -197,7 +197,7 @@ static struct clk_branch gpu_cc_cx_qdss_at_clk = { 


static struct clk_branch gpu_cc_cx_qdss_trig_clk = {

	.halt_reg = 0x1094,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1094,

		.enable_mask = BIT(0),
@@ -214,7 +214,7 @@ static struct clk_branch gpu_cc_cx_qdss_trig_clk = { 


static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {

	.halt_reg = 0x1084,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1084,

		.enable_mask = BIT(0),
@@ -231,7 +231,7 @@ static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { 


static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {

	.halt_reg = 0x108c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x108c,

		.enable_mask = BIT(0),
@@ -244,7 +244,7 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { 


static struct clk_branch gpu_cc_cxo_aon_clk = {

	.halt_reg = 0x1004,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1004,

		.enable_mask = BIT(0),
@@ -288,7 +288,7 @@ static struct clk_branch gpu_cc_gx_gmu_clk = { 


static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {

	.halt_reg = 0x105c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x105c,

		.enable_mask = BIT(0),
@@ -305,7 +305,7 @@ static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { 


static struct clk_branch gpu_cc_gx_vsense_clk = {

	.halt_reg = 0x1058,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1058,

		.enable_mask = BIT(0),
@@ -318,7 +318,7 @@ static struct clk_branch gpu_cc_gx_vsense_clk = { 


static struct clk_branch gpu_cc_sleep_clk = {

	.halt_reg = 0x1090,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x1090,

		.enable_mask = BIT(0),