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Commit 02a29480 authored by Chandan Uddaraju's avatar Chandan Uddaraju Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: fix register access path during device boot up 



During device boot up, MDP registers were directly accessed
using direct offset values. Fix this by adding new hardware
access operations for the needed hardware blocks.
For autorefresh configuration, use the existing
hardware operations.

Change-Id: I89aeac7946161fb6361654bc3ce533e3923e4842
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: default avatarSteve Cohen <cohens@codeaurora.org>
parent 2f5cb94f

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+31 −21
Original line number Diff line number Diff line
@@ -610,6 +610,35 @@ static void sde_hw_ctl_intf_cfg(struct sde_hw_ctl *ctx, 
	SDE_REG_WRITE(c, CTL_TOP, intf_cfg);

}



static inline u32 sde_hw_ctl_read_ctl_top(struct sde_hw_ctl *ctx)

{

	struct sde_hw_blk_reg_map *c;

	u32 ctl_top;



	if (!ctx) {

		pr_err("Invalid input argument\n");

		return 0;

	}

	c = &ctx->hw;

	ctl_top = SDE_REG_READ(c, CTL_TOP);

	return ctl_top;

}



static inline u32 sde_hw_ctl_read_ctl_layers(struct sde_hw_ctl *ctx, int index)

{

	struct sde_hw_blk_reg_map *c;

	u32 ctl_top;



	if (!ctx) {

		pr_err("Invalid input argument\n");

		return 0;

	}

	c = &ctx->hw;

	ctl_top = SDE_REG_READ(c, CTL_LAYER(index));

	pr_debug("Ctl_layer value = 0x%x\n", ctl_top);

	return ctl_top;

}



static void sde_hw_ctl_setup_sbuf_cfg(struct sde_hw_ctl *ctx,

	struct sde_ctl_sbuf_cfg *cfg)

{
@@ -640,6 +669,8 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
	ops->get_flush_register = sde_hw_ctl_get_flush_register;

	ops->trigger_start = sde_hw_ctl_trigger_start;

	ops->trigger_pending = sde_hw_ctl_trigger_pending;

	ops->read_ctl_top = sde_hw_ctl_read_ctl_top;

	ops->read_ctl_layers = sde_hw_ctl_read_ctl_layers;

	ops->setup_intf_cfg = sde_hw_ctl_intf_cfg;

	ops->reset = sde_hw_ctl_reset_control;

	ops->hard_reset = sde_hw_ctl_hard_reset;
@@ -663,27 +694,6 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
	}

};



#define CTL_BASE_OFFSET	0x2000

#define CTL_TOP_OFFSET(index) (CTL_BASE_OFFSET + (0x200 * (index)) + CTL_TOP)



void sde_get_ctl_top_for_cont_splash(void __iomem *mmio,

		struct ctl_top *top, int index)

{

	if (!mmio || !top) {

		SDE_ERROR("invalid input parameters\n");

		return;

	}



	top->value = readl_relaxed(mmio + CTL_TOP_OFFSET(index));

	top->intf_sel = (top->value >> 4) & 0xf;

	top->pp_sel = (top->value >> 8) & 0x7;

	top->dspp_sel = (top->value >> 11) & 0x3;

	top->mode_sel = (top->value >> 17) & 0x1;



	SDE_DEBUG("ctl[%d]_top->0x%x,pp_sel=0x%x,dspp_sel=0x%x,intf_sel=0x%x\n",

	       index, top->value, top->pp_sel, top->dspp_sel, top->intf_sel);

}



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

drivers/gpu/drm/msm/sde/sde_hw_ctl.h

+17 −9
Original line number Diff line number Diff line
@@ -200,6 +200,23 @@ struct sde_hw_ctl_ops { 
		u32 *flushbits,

		enum sde_rot blk);



	/**

	 * read CTL_TOP register value and return

	 * the data.

	 * @ctx		: ctl path ctx pointer

	 * @return	: CTL top register value

	 */

	u32 (*read_ctl_top)(struct sde_hw_ctl *ctx);



	/**

	 * read CTL layers register value and return

	 * the data.

	 * @ctx       : ctl path ctx pointer

	 * @index       : layer index for this ctl path

	 * @return	: CTL layers register value

	 */

	u32 (*read_ctl_layers)(struct sde_hw_ctl *ctx, int index);



	/**

	 * Set all blend stages to disabled

	 * @ctx       : ctl path ctx pointer
@@ -268,15 +285,6 @@ struct sde_hw_ctl { 
int sde_unstage_pipe_for_cont_splash(struct sde_splash_data *data,

		void __iomem *mmio);



/**

 * sde_get_ctl_top_for_cont_splash - retrieve the current LM blocks

 * @mmio: mapped register io address of MDP

 * @top: pointer to the current "ctl_top" structure thats needs update

 * @index: ctl_top index

 */

void sde_get_ctl_top_for_cont_splash(void __iomem *mmio,

		struct ctl_top *top, int index);



/**

 * sde_hw_ctl - convert base object sde_hw_base to container

 * @hw: Pointer to base hardware block

drivers/gpu/drm/msm/sde/sde_hw_lm.c

+0 −37
Original line number Diff line number Diff line
@@ -278,43 +278,6 @@ static void _setup_mixer_ops(struct sde_mdss_cfg *m, 
	}

};



#define CTL_BASE_OFFSET	0x2000

#define CTL_TOP_LM_OFFSET(index, lm)	\

	(CTL_BASE_OFFSET + (0x200 * index) + (lm * 0x4))



int sde_get_ctl_lm_for_cont_splash(void __iomem *mmio, int max_lm_cnt,

		u8 lm_cnt, u8 *lm_ids, struct ctl_top *top, int index)

{

	int j;

	struct sde_splash_lm_hw *lm;



	if (!mmio || !top || !lm_ids) {

		SDE_ERROR("invalid input parameters\n");

		return 0;

	}



	lm = top->lm;

	for (j = 0; j < max_lm_cnt; j++) {

		lm[top->ctl_lm_cnt].lm_reg_value = readl_relaxed(mmio

			      + CTL_TOP_LM_OFFSET(index, j));

		SDE_DEBUG("ctl[%d]_top --> lm[%d]=0x%x, j=%d\n",

			index, top->ctl_lm_cnt,

			lm[top->ctl_lm_cnt].lm_reg_value, j);

		SDE_DEBUG("lm_cnt = %d\n", lm_cnt);

		if (lm[top->ctl_lm_cnt].lm_reg_value) {

			lm[top->ctl_lm_cnt].ctl_id = index;

			lm_ids[lm_cnt++] = j + LM_0;

			lm[top->ctl_lm_cnt].lm_id = j + LM_0;

			SDE_DEBUG("ctl_id=%d, lm[%d].lm_id = %d\n",

				lm[top->ctl_lm_cnt].ctl_id,

				top->ctl_lm_cnt,

				lm[top->ctl_lm_cnt].lm_id);

			top->ctl_lm_cnt++;

		}

	}

	return top->ctl_lm_cnt;

}



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

drivers/gpu/drm/msm/sde/sde_hw_lm.h

+0 −13
Original line number Diff line number Diff line
@@ -116,19 +116,6 @@ static inline struct sde_hw_mixer *to_sde_hw_mixer(struct sde_hw_blk *hw) 
	return container_of(hw, struct sde_hw_mixer, base);

}



/**

 * sde_get_ctl_lm_for_cont_splash - retrieve the current LM blocks

 * @mmio: mapped register io address of MDP

 * @max_lm_cnt: number of LM blocks supported in the hw

 * @lm_cnt: number of LM blocks already active

 * @lm_ids: pointer to store the active LM block IDs

 * @top: pointer to the current "ctl_top" structure

 * @index: ctl_top index

 * return: number of active LM blocks for this CTL block

 */

int sde_get_ctl_lm_for_cont_splash(void __iomem *mmio, int max_lm_cnt,

		u8 lm_cnt, u8 *lm_ids, struct ctl_top *top, int index);



/**

 * sde_hw_lm_init(): Initializes the mixer hw driver object.

 * should be called once before accessing every mixer.

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+2 −0
Original line number Diff line number Diff line
@@ -581,6 +581,7 @@ struct ctl_top { 
 * @ctl_top_cnt:stores the active number of MDSS "top" blks of the current mode

 * @lm_cnt:	stores the active number of MDSS "LM" blks for the current mode

 * @dsc_cnt:	stores the active number of MDSS "dsc" blks for the current mode

 * @cont_splash_en:	Stores the cont_splash status (enabled/disabled)

 */

struct sde_splash_data {

	bool smmu_handoff_pending;
@@ -593,6 +594,7 @@ struct sde_splash_data { 
	u8 ctl_top_cnt;

	u8 lm_cnt;

	u8 dsc_cnt;

	bool cont_splash_en;

};



#endif  /* _SDE_HW_MDSS_H */