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Commit 007d05d8 authored by Gregory CLEMENT's avatar Gregory CLEMENT
Browse files

ARM: dts: armada-xp: Fixup pcie DT warnings



PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 1fc21295
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+22 −22
Original line number Diff line number Diff line
@@ -73,28 +73,6 @@
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		pcie-controller {
			status = "okay";

			/* First mini-PCIe port */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/* Second mini-PCIe port */
			pcie@2,0 {
				/* Port 0, Lane 1 */
				status = "okay";
			};

			/* Renesas uPD720202 USB 3.0 controller */
			pcie@3,0 {
				/* Port 0, Lane 3 */
				status = "okay";
			};
		};

		internal-regs {
			/* UART0 */
			serial@12000 {
@@ -153,6 +131,28 @@
	};
};

&pciec {
	status = "okay";

	/* First mini-PCIe port */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* Second mini-PCIe port */
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};

	/* Renesas uPD720202 USB 3.0 controller */
	pcie@3,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
};

&pinctrl {
	pinctrl-0 = <&phy_int_pin>;
	pinctrl-names = "default";
+33 −33
Original line number Diff line number Diff line
@@ -108,39 +108,6 @@
			};
		};

		pcie-controller {
			status = "okay";

			/*
			 * All 6 slots are physically present as
			 * standard PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};
			pcie@2,0 {
				/* Port 0, Lane 1 */
				status = "okay";
			};
			pcie@3,0 {
				/* Port 0, Lane 2 */
				status = "okay";
			};
			pcie@4,0 {
				/* Port 0, Lane 3 */
				status = "okay";
			};
			pcie@9,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
			pcie@10,0 {
				/* Port 3, Lane 0 */
				status = "okay";
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
@@ -248,6 +215,39 @@
	};
};

&pciec {
	status = "okay";

	/*
	 * All 6 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};
	pcie@3,0 {
		/* Port 0, Lane 2 */
		status = "okay";
	};
	pcie@4,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@10,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
+21 −21
Original line number Diff line number Diff line
@@ -127,27 +127,6 @@
			};
		};

		pcie-controller {
			status = "okay";

			/*
			 * The 3 slots are physically present as
			 * standard PCIe slots on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};
			pcie@9,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
			pcie@10,0 {
				/* Port 3, Lane 0 */
				status = "okay";
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
@@ -233,6 +212,27 @@
	};
};

&pciec {
	status = "okay";

	/*
	 * The 3 slots are physically present as
	 * standard PCIe slots on the board.
	 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};
	pcie@9,0 {
		/* Port 2, Lane 0 */
		status = "okay";
	};
	pcie@10,0 {
		/* Port 3, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 {
		reg = <16>;
+15 −16
Original line number Diff line number Diff line
@@ -68,22 +68,6 @@
			MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		pcie-controller {
			status = "okay";

			/* Quad port sata: Marvell 88SX7042 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/* USB 3.0 xHCI controller: NEC D720200F1 */
			pcie@5,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};
		};

		internal-regs {
			serial@12000 {
				status = "okay";
@@ -285,6 +269,21 @@
		gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
	};
};
&pciec {
	status = "okay";

	/* Quad port sata: Marvell 88SX7042 */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* USB 3.0 xHCI controller: NEC D720200F1 */
	pcie@5,0 {
		/* Port 1, Lane 0 */
		status = "okay";
	};
};

&mdio {
	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
+22 −22
Original line number Diff line number Diff line
@@ -73,28 +73,6 @@
			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;

		pcie-controller {
			status = "okay";

			/* Etron EJ168 USB 3.0 controller */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/* First mini-PCIe port */
			pcie@2,0 {
				/* Port 0, Lane 1 */
				status = "okay";
			};

			/* Second mini-PCIe port */
			pcie@3,0 {
				/* Port 0, Lane 3 */
				status = "okay";
			};
		};

		internal-regs {

			rtc@10300 {
@@ -369,6 +347,28 @@
	};
};

&pciec {
	status = "okay";

	/* Etron EJ168 USB 3.0 controller */
	pcie@1,0 {
		/* Port 0, Lane 0 */
		status = "okay";
	};

	/* First mini-PCIe port */
	pcie@2,0 {
		/* Port 0, Lane 1 */
		status = "okay";
	};

	/* Second mini-PCIe port */
	pcie@3,0 {
		/* Port 0, Lane 3 */
		status = "okay";
	};
};

&pinctrl {

	keys_pin: keys-pin {
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