Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0000452d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add support for META MI2S ports"

parents c3d71b92 368668cc

Documentation/devicetree/bindings/sound/qcom-audio-dev.txt

+30 −0
Original line number Diff line number Diff line
@@ -838,6 +838,36 @@ qcom,msm-dai-mi2s { 
		};

};



* msm-dai-q6-meta-mi2s



Required properties:



- compatible : "qcom,msm-dai-q6-meta-mi2s"

- qcom,msm-dai-q6-meta-mi2s-dev-id: This section is used by CPU driver in ASOC

				to configure META-MI2S interface which provides

				the capability to group seversl MI2S interfaces

				into a single device.

				They are represented with dev-id 4864 and 4866.



- qcom,msm-mi2s-num-members:	Specifies how many MI2S interfaces are grouped.



- qcom,msm-mi2s-member-id:	List dev-id for each member MI2S interface.



- qcom,msm-mi2s-rx-lines:	Specify the number of SD lines for each member

				MI2S interface.

				This element indicates which output RX lines

				are used in the META-MI2S interface.



Example:



qcom,msm-dai-q6-meta-mi2s-prim {

	compatible = "qcom,msm-dai-q6-meta-mi2s";

	qcom,msm-dai-q6-mi2s-dev-id = <4864>;

	qcom,msm-mi2s-num-members = <2>;

	qcom,msm-mi2s-member-id = <0>, <1>;

	qcom,msm-mi2s-rx-lines = <0xf>, <0xf>;

};



* msm-dai-spdif



[First Level Nodes]

arch/arm64/boot/dts/qcom/msm-audio-lpass.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -147,6 +147,22 @@ 
		};

	};



	dai_meta_mi2s0: qcom,msm-dai-q6-meta-mi2s-prim {

		compatible = "qcom,msm-dai-q6-meta-mi2s";

		qcom,msm-dai-q6-meta-mi2s-dev-id = <4864>;

		qcom,msm-mi2s-num-members = <4>;

		qcom,msm-mi2s-member-id = <0>, <1>, <2>, <3>;

		qcom,msm-mi2s-rx-lines = <0xff>, <0xf>, <0x3>, <0x3>;

	};



	dai_meta_mi2s1: qcom,msm-dai-q6-meta-mi2s-sec {

		compatible = "qcom,msm-dai-q6-meta-mi2s";

		qcom,msm-dai-q6-meta-mi2s-dev-id = <4866>;

		qcom,msm-mi2s-num-members = <4>;

		qcom,msm-mi2s-member-id = <0>, <1>, <2>, <3>;

		qcom,msm-mi2s-rx-lines = <0xff>, <0xf>, <0x3>, <0x3>;

	};



	msm_dai_cdc_dma: qcom,msm-dai-cdc-dma {

		compatible = "qcom,msm-dai-cdc-dma";

		wsa_cdc_dma_0_rx: qcom,msm-dai-wsa-cdc-dma-0-rx {

arch/arm64/boot/dts/qcom/qcs405-audio.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ 
				"msm-pcm-dsp-noirq", "msm-transcode-loopback";

		asoc-cpu = <&dai_dp>, <&dai_mi2s0>, <&dai_mi2s1>,

			<&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s4>, <&dai_mi2s5>,

			<&dai_meta_mi2s0>, <&dai_meta_mi2s1>,

			<&dai_pri_auxpcm>, <&dai_sec_auxpcm>,

			<&dai_tert_auxpcm>, <&dai_quat_auxpcm>,

			<&dai_quin_auxpcm>,
@@ -118,6 +119,8 @@ 
			"msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",

			"msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",

			"msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",

			"msm-dai-q6-meta-mi2s.4864",

			"msm-dai-q6-meta-mi2s.4866",

			"msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",

			"msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4",

			"msm-dai-q6-auxpcm.5",

arch/arm64/boot/dts/qcom/qcs405-csra8plus2-audio-overlay.dtsi

0 → 100644
+179 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&q6core {

	cdc_dmic01_gpios: cdc_dmic01_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;

		pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;

		qcom,lpi-gpios;

	};



	cdc_dmic23_gpios: cdc_dmic23_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;

		pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;

		qcom,lpi-gpios;

	};



	cdc_dmic45_gpios: cdc_dmic45_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;

		pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;

		qcom,lpi-gpios;

	};



	cdc_dmic67_gpios: cdc_dmic67_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;

		pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;

		qcom,lpi-gpios;

	};



	pri_mi2s_gpios: pri_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&pri_mi2s_sck_active &pri_mi2s_ws_active

		&pri_mi2s_sd0_active &pri_mi2s_sd1_active

		&pri_mi2s_sd2_active &pri_mi2s_sd3_active

		&pri_mi2s_sd4_active &pri_mi2s_sd5_active

		&pri_mi2s_sd6_active &pri_mi2s_sd7_active>;

		pinctrl-1 = <&pri_mi2s_sck_sleep &pri_mi2s_ws_sleep

		&pri_mi2s_sd0_sleep &pri_mi2s_sd1_sleep

		&pri_mi2s_sd2_sleep &pri_mi2s_sd3_sleep

		&pri_mi2s_sd4_sleep &pri_mi2s_sd5_sleep

		&pri_mi2s_sd6_sleep &pri_mi2s_sd7_sleep>;

	};



	sec_mi2s_gpios: sec_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&sec_mi2s_sck_active &sec_mi2s_ws_active

		&sec_mi2s_sd0_active &sec_mi2s_sd1_active

		&sec_mi2s_sd2_active &sec_mi2s_sd3_active>;

		pinctrl-1 = <&sec_mi2s_sck_sleep &sec_mi2s_ws_sleep

		&sec_mi2s_sd0_sleep &sec_mi2s_sd1_sleep

		&sec_mi2s_sd2_sleep &sec_mi2s_sd3_sleep>;

	};



	quat_mi2s_gpios: quat_mi2s_pinctrl {

		compatible = "qcom,msm-cdc-pinctrl";

		pinctrl-names = "aud_active", "aud_sleep";

		pinctrl-0 = <&quat_mi2s_sck_active &quat_mi2s_ws_active

		&quat_mi2s_sd0_active &quat_mi2s_sd1_active>;

		pinctrl-1 = <&quat_mi2s_sck_sleep &quat_mi2s_ws_sleep

		&quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>;

	};

};



&q6core {

	bolero: bolero-cdc {

		compatible = "qcom,bolero-codec";

		clock-names = "lpass_core_hw_vote";

		clocks = <&lpass_core_hw_vote 0>;

		qcom,num-macros = <1>;

	};

};



&qcs405_snd {

	qcom,model = "qcs405-csra8plus2-snd-card";

	qcom,meta-mi2s-intf = <1>;

	qcom,va-bolero-codec = <1>;

	qcom,tasha-codec = <1>;

	qcom,csra-codec = <1>;

	asoc-codec = <&stub_codec>, <&bolero>;

	asoc-codec-names = "msm-stub-codec.1", "bolero_codec";

	qcom,csra-max-devs = <8>;

	qcom,csra-devs = <&csra66x0_ampl_6B>, <&csra66x0_ampl_6A>,

		<&csra66x0_ampl_69>, <&csra66x0_ampl_68>,

		<&csra66x0_ampl_6B_1>, <&csra66x0_ampl_6A_1>,

		<&csra66x0_ampl_69_1>, <&csra66x0_ampl_68_1>;

	qcom,csra-aux-dev-prefix = "CSRA_78", "CSRA_56", "CSRA_34",

		"CSRA_12", "CSRA_F0", "CSRA_DE", "CSRA_BC", "CSRA_9A";

	qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;

	qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;

	qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;

	qcom,cdc-dmic67-gpios = <&cdc_dmic67_gpios>;

	qcom,pri-mi2s-gpios = <&pri_mi2s_gpios>;

	qcom,sec-mi2s-gpios = <&sec_mi2s_gpios>;

	qcom,quat-mi2s-gpios = <&quat_mi2s_gpios>;

	qcom,msm-mi2s-master = <1>, <0>, <1>, <0>, <1>, <1>;

	qcom,audio-routing =

		"RX_BIAS", "MCLK",

		"lineout booster", "LINEOUT1",

		"lineout booster", "LINEOUT2",

		"LINEOUT1", "rx regulator",

		"LINEOUT2", "rx regulator",

		"AMIC3", "tx regulator",

		"AMIC4", "tx regulator",

		"AMIC3", "MIC BIAS3",

		"AMIC4", "MIC BIAS4",

		"MIC BIAS3", "Analog Mic3",

		"MIC BIAS4", "Analog Mic4",

		"VA DMIC0", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic0",

		"VA DMIC1", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic1",

		"VA DMIC2", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic2",

		"VA DMIC3", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic3",

		"VA DMIC4", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic4",

		"VA DMIC5", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic5",

		"VA DMIC6", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic6",

		"VA DMIC7", "VA MIC BIAS1",

		"VA MIC BIAS1", "Digital Mic7",

		"CSRA_12 IN", "PRI_META_MI2S_RX",

		"CSRA_34 IN", "PRI_META_MI2S_RX",

		"CSRA_56 IN", "PRI_META_MI2S_RX",

		"CSRA_78 IN", "PRI_META_MI2S_RX",

		"CSRA_9A IN", "PRI_META_MI2S_RX",

		"CSRA_BC IN", "PRI_META_MI2S_RX",

		"CSRA_DE IN", "PRI_META_MI2S_RX",

		"CSRA_F0 IN", "PRI_META_MI2S_RX";

	pinctrl-names = "default";

	pinctrl-0 = <&spdifrx_opt_default>;

};



&dai_mi2s0 {

	qcom,msm-mi2s-rx-lines = <0xff>;

};



&dai_meta_mi2s0 {

	qcom,msm-mi2s-num-members =  <2>;

	qcom,msm-mi2s-member-id =  <0>, <3>;

	qcom,msm-mi2s-rx-lines = <0xff>, <0x03>;

};



#include "qcs405-tasha.dtsi"

#include "qcs405-va-bolero.dtsi"

#include "qcs405-csra8.dtsi"



&lineout_booster_gpio {

	status = "disabled";

};



&lineout_booster_sleep {

	status = "disabled";

};



&lineout_booster_active {

	status = "disabled";

};

arch/arm64/boot/dts/qcom/qcs405-pinctrl.dtsi

+231 −0
Original line number Diff line number Diff line
@@ -2030,6 +2030,237 @@ 
			};

		};



		quat_mi2s_sck {

			quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {

				mux {

					pins = "gpio110";

					function = "i2s_4";

				};



				config {

					pins = "gpio110";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sck_active: quat_mi2s_sck_active {

				mux {

					pins = "gpio110";

					function = "i2s_4";

				};



				config {

					pins = "gpio110";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_ws {

			quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {

				mux {

					pins = "gpio111";

					function = "i2s_4";

				};



				config {

					pins = "gpio111";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_ws_active: quat_mi2s_ws_active {

				mux {

					pins = "gpio111";

					function = "i2s_4";

				};



				config {

					pins = "gpio111";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_sd0 {

			quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {

				mux {

					pins = "gpio112";

					function = "i2s_4";

				};



				config {

					pins = "gpio112";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd0_active: quat_mi2s_sd0_active {

				mux {

					pins = "gpio112";

					function = "i2s_4";

				};



				config {

					pins = "gpio112";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_sd1 {

			quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {

				mux {

					pins = "gpio113";

					function = "i2s_4";

				};



				config {

					pins = "gpio113";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd1_active: quat_mi2s_sd1_active {

				mux {

					pins = "gpio113";

					function = "i2s_4";

				};



				config {

					pins = "gpio113";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};

		quat_mi2s_sd2 {

			quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {

				mux {

					pins = "gpio114";

					function = "i2s_4";

				};



				config {

					pins = "gpio114";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd2_active: quat_mi2s_sd2_active {

				mux {

					pins = "gpio114";

					function = "i2s_4";

				};



				config {

					pins = "gpio114";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_sd3 {

			quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {

				mux {

					pins = "gpio115";

					function = "i2s_4";

				};



				config {

					pins = "gpio115";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd3_active: quat_mi2s_sd3_active {

				mux {

					pins = "gpio115";

					function = "i2s_4";

				};



				config {

					pins = "gpio115";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_sd4 {

			quat_mi2s_sd4_sleep: quat_mi2s_sd4_sleep {

				mux {

					pins = "gpio116";

					function = "i2s_4";

				};



				config {

					pins = "gpio116";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd4_active: quat_mi2s_sd4_active {

				mux {

					pins = "gpio116";

					function = "i2s_4";

				};



				config {

					pins = "gpio116";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		quat_mi2s_sd5 {

			quat_mi2s_sd5_sleep: quat_mi2s_sd5_sleep {

				mux {

					pins = "gpio117";

					function = "i2s_4";

				};



				config {

					pins = "gpio117";

					drive-strength = <2>;   /* 2 mA */

					bias-pull-down;         /* PULL DOWN */

					input-enable;

				};

			};



			quat_mi2s_sd5_active: quat_mi2s_sd5_active {

				mux {

					pins = "gpio117";

					function = "i2s_4";

				};



				config {

					pins = "gpio117";

					drive-strength = <8>;   /* 8 mA */

					bias-disable;           /* NO PULL */

				};

			};

		};



		/* SPDIF optical input pin */

		spdifrx_opt {

			spdifrx_opt_default: spdifrx_opt_default {