Loading drivers/platform/msm/ep_pcie/ep_pcie_core.c +5 −1 Original line number Diff line number Diff line Loading @@ -591,8 +591,12 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK)); } if (dev->active_config) if (dev->active_config) { ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14); EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1.\n", dev->rev); ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); } } static void ep_pcie_config_inbound_iatu(struct ep_pcie_dev_t *dev) Loading Loading
drivers/platform/msm/ep_pcie/ep_pcie_core.c +5 −1 Original line number Diff line number Diff line Loading @@ -591,8 +591,12 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) readl_relaxed(dev->parf + PCIE20_PARF_INT_ALL_MASK)); } if (dev->active_config) if (dev->active_config) { ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14); EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1.\n", dev->rev); ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); } } static void ep_pcie_config_inbound_iatu(struct ep_pcie_dev_t *dev) Loading