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Commit ff401e52 authored by Steven J. Hill's avatar Steven J. Hill
Browse files

MIPS: Optimise TLB handlers for MIPS32/64 R2 cores. 



The EXT and INS instructions can be used to decrease code size and
thus speed up TLB handlers on MIPS32R2 and MIPS64R2 cores.

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
parent e6de1a09

arch/mips/mm/tlbex.c

+16 −0
Original line number Diff line number Diff line
@@ -933,6 +933,13 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 
#endif

	uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */

	uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);



	if (cpu_has_mips_r2) {

		uasm_i_ext(p, tmp, tmp, PGDIR_SHIFT, (32 - PGDIR_SHIFT));

		uasm_i_ins(p, ptr, tmp, PGD_T_LOG2, (32 - PGDIR_SHIFT));

		return;

	}



	uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */

	uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);

	uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
@@ -968,6 +975,15 @@ static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) 


static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)

{

	if (cpu_has_mips_r2) {

		/* PTE ptr offset is obtained from BadVAddr */

		UASM_i_MFC0(p, tmp, C0_BADVADDR);

		UASM_i_LW(p, ptr, 0, ptr);

		uasm_i_ext(p, tmp, tmp, PAGE_SHIFT+1, PGDIR_SHIFT-PAGE_SHIFT-1);

		uasm_i_ins(p, ptr, tmp, PTE_T_LOG2+1, PGDIR_SHIFT-PAGE_SHIFT-1);

		return;

	}



	/*

	 * Bug workaround for the Nevada. It seems as if under certain

	 * circumstances the move from cp0_context might produce a