Loading drivers/gpu/msm/a5xx_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,9 @@ #define A5XX_CP_PFP_STAT_DATA 0x809 #define A5XX_CP_DRAW_STATE_ADDR 0x80B #define A5XX_CP_DRAW_STATE_DATA 0x80C #define A5XX_CP_CRASH_SCRIPT_BASE_LO 0x817 #define A5XX_CP_CRASH_SCRIPT_BASE_HI 0x818 #define A5XX_CP_CRASH_DUMP_CNTL 0x819 #define A5XX_CP_ME_STAT_ADDR 0x81A #define A5XX_CP_ROQ_THRESHOLDS_1 0x81F #define A5XX_CP_ROQ_THRESHOLDS_2 0x820 Loading drivers/gpu/msm/adreno.c +2 −0 Original line number Diff line number Diff line Loading @@ -1339,6 +1339,8 @@ static int adreno_init(struct kgsl_device *device) if (gpudev->preemption_init && adreno_is_preemption_enabled(adreno_dev)) gpudev->preemption_init(adreno_dev); if (gpudev->cp_crash_dumper_init) gpudev->cp_crash_dumper_init(adreno_dev); return 0; } Loading drivers/gpu/msm/adreno.h +5 −0 Original line number Diff line number Diff line Loading @@ -343,6 +343,10 @@ struct adreno_device { struct kgsl_memdesc preemption_counters; struct work_struct gpmu_work; uint32_t lm_leakage; struct kgsl_memdesc capturescript; struct kgsl_memdesc snapshot_registers; bool capturescript_working; }; /** Loading Loading @@ -678,6 +682,7 @@ struct adreno_gpudev { void (*preemption_init)(struct adreno_device *); void (*preemption_schedule)(struct adreno_device *); void (*enable_64bit)(struct adreno_device *); void (*cp_crash_dumper_init)(struct adreno_device *); }; struct log_field { Loading drivers/gpu/msm/adreno_a5xx.c +15 −0 Original line number Diff line number Diff line Loading @@ -1535,6 +1535,20 @@ out: mutex_unlock(&device->mutex); } /* * a5xx_cp_crash_dumper_init() - Initialize CP Crash Dumper. Allocate memory * for capturescript and for register dump * @adreno_dev: Pointer to adreno device */ static void a5xx_cp_crash_dumper_init(struct adreno_device *adreno_dev) { kgsl_allocate_global(&adreno_dev->dev, &adreno_dev->capturescript, PAGE_SIZE, KGSL_MEMFLAGS_GPUREADONLY, 0); kgsl_allocate_global(&adreno_dev->dev, &adreno_dev->snapshot_registers, a5xx_num_registers() * 4, 0 , 0); adreno_dev->capturescript_working = true; } /* * a5xx_start() - Device start * @adreno_dev: Pointer to adreno device Loading Loading @@ -3279,4 +3293,5 @@ struct adreno_gpudev adreno_a5xx_gpudev = { .preemption_init = a5xx_preemption_init, .preemption_schedule = a5xx_preemption_schedule, .enable_64bit = a5xx_enable_64bit, .cp_crash_dumper_init = a5xx_cp_crash_dumper_init, }; drivers/gpu/msm/adreno_a5xx.h +1 −0 Original line number Diff line number Diff line Loading @@ -70,5 +70,6 @@ struct a5xx_cp_smmu_info { void a5xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_snapshot *snapshot); unsigned int a5xx_num_registers(void); #endif Loading
drivers/gpu/msm/a5xx_reg.h +3 −0 Original line number Diff line number Diff line Loading @@ -66,6 +66,9 @@ #define A5XX_CP_PFP_STAT_DATA 0x809 #define A5XX_CP_DRAW_STATE_ADDR 0x80B #define A5XX_CP_DRAW_STATE_DATA 0x80C #define A5XX_CP_CRASH_SCRIPT_BASE_LO 0x817 #define A5XX_CP_CRASH_SCRIPT_BASE_HI 0x818 #define A5XX_CP_CRASH_DUMP_CNTL 0x819 #define A5XX_CP_ME_STAT_ADDR 0x81A #define A5XX_CP_ROQ_THRESHOLDS_1 0x81F #define A5XX_CP_ROQ_THRESHOLDS_2 0x820 Loading
drivers/gpu/msm/adreno.c +2 −0 Original line number Diff line number Diff line Loading @@ -1339,6 +1339,8 @@ static int adreno_init(struct kgsl_device *device) if (gpudev->preemption_init && adreno_is_preemption_enabled(adreno_dev)) gpudev->preemption_init(adreno_dev); if (gpudev->cp_crash_dumper_init) gpudev->cp_crash_dumper_init(adreno_dev); return 0; } Loading
drivers/gpu/msm/adreno.h +5 −0 Original line number Diff line number Diff line Loading @@ -343,6 +343,10 @@ struct adreno_device { struct kgsl_memdesc preemption_counters; struct work_struct gpmu_work; uint32_t lm_leakage; struct kgsl_memdesc capturescript; struct kgsl_memdesc snapshot_registers; bool capturescript_working; }; /** Loading Loading @@ -678,6 +682,7 @@ struct adreno_gpudev { void (*preemption_init)(struct adreno_device *); void (*preemption_schedule)(struct adreno_device *); void (*enable_64bit)(struct adreno_device *); void (*cp_crash_dumper_init)(struct adreno_device *); }; struct log_field { Loading
drivers/gpu/msm/adreno_a5xx.c +15 −0 Original line number Diff line number Diff line Loading @@ -1535,6 +1535,20 @@ out: mutex_unlock(&device->mutex); } /* * a5xx_cp_crash_dumper_init() - Initialize CP Crash Dumper. Allocate memory * for capturescript and for register dump * @adreno_dev: Pointer to adreno device */ static void a5xx_cp_crash_dumper_init(struct adreno_device *adreno_dev) { kgsl_allocate_global(&adreno_dev->dev, &adreno_dev->capturescript, PAGE_SIZE, KGSL_MEMFLAGS_GPUREADONLY, 0); kgsl_allocate_global(&adreno_dev->dev, &adreno_dev->snapshot_registers, a5xx_num_registers() * 4, 0 , 0); adreno_dev->capturescript_working = true; } /* * a5xx_start() - Device start * @adreno_dev: Pointer to adreno device Loading Loading @@ -3279,4 +3293,5 @@ struct adreno_gpudev adreno_a5xx_gpudev = { .preemption_init = a5xx_preemption_init, .preemption_schedule = a5xx_preemption_schedule, .enable_64bit = a5xx_enable_64bit, .cp_crash_dumper_init = a5xx_cp_crash_dumper_init, };
drivers/gpu/msm/adreno_a5xx.h +1 −0 Original line number Diff line number Diff line Loading @@ -70,5 +70,6 @@ struct a5xx_cp_smmu_info { void a5xx_snapshot(struct adreno_device *adreno_dev, struct kgsl_snapshot *snapshot); unsigned int a5xx_num_registers(void); #endif