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Commit fe955e5c authored by Prarit Bhargava's avatar Prarit Bhargava Committed by Ingo Molnar
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x86: nmi: Add Intel processor 0x6f4 to NMI perfctr1 workaround 



Expand Intel NMI perfctr1 workaround to include a Core2 processor stepping
(cpuid family-6, model-f, stepping-4).  Resolves a situation where the NMI
would not enable on these processors.

Signed-off-by: default avatarPrarit Bhargava <prarit@redhat.com>
Acked-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
Cc: prarit@redhat.com
Cc: suresh.b.siddha@intel.com
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 8f7007aa

arch/x86/kernel/cpu/perfctr-watchdog.c

+8 −4
Original line number Diff line number Diff line
@@ -716,11 +716,15 @@ static void probe_nmi_watchdog(void) 
		wd_ops = &k7_wd_ops;

		break;

	case X86_VENDOR_INTEL:

		/*

		 * Work around Core Duo (Yonah) errata AE49 where perfctr1

		 * doesn't have a working enable bit.

		/* Work around where perfctr1 doesn't have a working enable

		 * bit as described in the following errata:

		 * AE49 Core Duo and Intel Core Solo 65 nm

		 * AN49 Intel Pentium Dual-Core

		 * AF49 Dual-Core Intel Xeon Processor LV

		 */

		if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) {

		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) ||

		    ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 15 &&

		     boot_cpu_data.x86_mask == 4))) {

			intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;

			intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;

		}