ARM: dts: msm: configure VDD_APCC CPR for HMSS alternate PLL on msm8996v3

Using the alternate as opposed to the primary PLL for the HMSS
power and performance clusters on MSM8996v3 imposes several
restrictions for VDD_APCC CPR.  The first is that the alternate
PLL requires a minimum VDD_APCC supply voltage of 680 mV when
either cluster is operating above 750 MHz.  The second is that
CPR clock throttling cannot be used in conjunction with the
alternate PLL.

Update the VDD_APCC CPR floor voltages for the power and
performance cluster regulators so that the HMSS alternate PLL may
be used.  Disable CPR clock throttling.  Also disable closed-loop
CPR operation to ensure safe execution when the performance
cluster resumes from L2 power collapse with clock throttling
disabled.

Change-Id: I3c11da02b7698880d0f40d678b047f549163d4c4
Signed-off-by: David Collins <collinsd@codeaurora.org>