Merge "clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate" (fe2e14fd) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-alpha-pll.c

+9 −2

Original line number	Diff line number	Diff line
		@@ -611,13 +611,17 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate)
		return -EINVAL;
		}

		if (pll->no_irq_dis)
		spin_lock(&c->lock);
		else
		spin_lock_irqsave(&c->lock, flags);

		/*
		* For PLLs that do not support dynamic programming (dynamic_update
		* is not set), ensure PLL is off before changing rate. For
		* optimization reasons, assume no downstream clock is actively
		* using it.
		*/
		spin_lock_irqsave(&c->lock, flags);
		if (c->count && !pll->dynamic_update)
		c->ops->disable(c);

		@@ -643,6 +647,9 @@ static int alpha_pll_set_rate(struct clk *c, unsigned long rate)
		if (c->count && !pll->dynamic_update)
		c->ops->enable(c);

		if (pll->no_irq_dis)
		spin_unlock(&c->lock);
		else
		spin_unlock_irqrestore(&c->lock, flags);
		return 0;
		}

+2 −0

Original line number	Diff line number	Diff line
		@@ -238,6 +238,7 @@ static struct alpha_pll_clk perfcl_alt_pll = {
		.post_div_config = 0x100, /* Div-2 */
		.config_ctl_val = 0x4001051B,
		.offline_bit_workaround = true,
		.no_irq_dis = true,
		.c = {
		.always_on = true,
		.parent = &alpha_xo_ao.c,
		@@ -300,6 +301,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = {
		.post_div_config = 0x100, /* Div-2 */
		.config_ctl_val = 0x4001051B,
		.offline_bit_workaround = true,
		.no_irq_dis = true,
		.c = {
		.always_on = true,
		.dbg_name = "pwrcl_alt_pll",

+1 −0

Original line number	Diff line number	Diff line
		@@ -79,6 +79,7 @@ struct alpha_pll_clk {
		* that the workaround is required.
		*/
		bool offline_bit_workaround;
		bool no_irq_dis;
		bool is_fabia;
		unsigned long min_supported_freq;
		struct clk c;