Loading arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -286,6 +286,7 @@ 0x828000 0x828000 0x108>; qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; qcom,timing-db-mode; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, Loading drivers/video/msm/mdss/mdss_dsi.c +2 −3 Original line number Diff line number Diff line Loading @@ -1512,7 +1512,7 @@ int mdss_dsi_cont_splash_on(struct mdss_panel_data *pdata) static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata, int new_fps) { u32 hsync_period, vsync_period, ctrl_rev; u32 hsync_period, vsync_period; u32 new_dsi_v_total, current_dsi_v_total; struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; Loading Loading @@ -1548,8 +1548,7 @@ static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata, MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C, (new_dsi_v_total & 0x7ffffff)); } ctrl_rev = MIPI_INP(ctrl_pdata->ctrl_base); /* Flush DSI TIMING registers for 8916/8939 */ if (ctrl_pdata->shared_data->timing_db_mode) MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1); ctrl_pdata->panel_data.panel_info.mipi.frame_rate = new_fps; Loading Loading
arch/arm/boot/dts/qcom/msm8996-mdss.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -286,6 +286,7 @@ 0x828000 0x828000 0x108>; qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; qcom,timing-db-mode; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, Loading
drivers/video/msm/mdss/mdss_dsi.c +2 −3 Original line number Diff line number Diff line Loading @@ -1512,7 +1512,7 @@ int mdss_dsi_cont_splash_on(struct mdss_panel_data *pdata) static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata, int new_fps) { u32 hsync_period, vsync_period, ctrl_rev; u32 hsync_period, vsync_period; u32 new_dsi_v_total, current_dsi_v_total; struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; Loading Loading @@ -1548,8 +1548,7 @@ static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata, MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C, (new_dsi_v_total & 0x7ffffff)); } ctrl_rev = MIPI_INP(ctrl_pdata->ctrl_base); /* Flush DSI TIMING registers for 8916/8939 */ if (ctrl_pdata->shared_data->timing_db_mode) MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1); ctrl_pdata->panel_data.panel_info.mipi.frame_rate = new_fps; Loading