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Commit fdd8b079 authored by Nicolas Pitre's avatar Nicolas Pitre Committed by Russell King
Browse files

[ARM] 5460/1: Orion: reduce namespace pollution 



Symbols like SOFT_RESET are way too generic to be exported at large.
To avoid this, let's move the mbus bridge register defines into a
separate file and include it where needed.  This affects mach-kirkwood,
mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
share code in plat-orion which relies on those defines.

Some other defines have been moved to narrower scopes, or simply deleted
when they had no user.

This fixes compilation problem with mpt2sas on the above listed
platforms.

Signed-off-by: default avatarNicolas Pitre <nico@marvell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent ae1036a2

arch/arm/mach-kirkwood/common.c

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <asm/mach/map.h>

#include <asm/mach/time.h>

#include <mach/kirkwood.h>

#include <mach/bridge-regs.h>

#include <plat/cache-feroceon-l2.h>

#include <plat/ehci-orion.h>

#include <plat/mvsdio.h>

arch/arm/mach-kirkwood/include/mach/bridge-regs.h

0 → 100644
+42 −0
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-kirkwood/include/mach/bridge-regs.h

 *

 * Mbus-L to Mbus Bridge Registers

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#ifndef __ASM_ARCH_BRIDGE_REGS_H

#define __ASM_ARCH_BRIDGE_REGS_H



#include <mach/kirkwood.h>



#define CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)

#define CPU_RESET		0x00000002



#define RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)

#define SOFT_RESET_OUT_EN	0x00000004



#define SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)

#define SOFT_RESET		0x00000001



#define BRIDGE_CAUSE		(BRIDGE_VIRT_BASE | 0x0110)

#define BRIDGE_MASK		(BRIDGE_VIRT_BASE | 0x0114)

#define BRIDGE_INT_TIMER0	0x0002

#define BRIDGE_INT_TIMER1	0x0004

#define BRIDGE_INT_TIMER1_CLR	(~0x0004)



#define IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)

#define IRQ_CAUSE_LOW_OFF	0x0000

#define IRQ_MASK_LOW_OFF	0x0004

#define IRQ_CAUSE_HIGH_OFF	0x0010

#define IRQ_MASK_HIGH_OFF	0x0014



#define TIMER_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0300)



#define L2_CONFIG_REG		(BRIDGE_VIRT_BASE | 0x0128)

#define L2_WRITETHROUGH		0x00000010



#endif

arch/arm/mach-kirkwood/include/mach/debug-macro.S

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
 * published by the Free Software Foundation.

*/



#include <mach/kirkwood.h>

#include <mach/bridge-regs.h>



	.macro	addruart,rx

	mrc	p15, 0, \rx, c1, c0

arch/arm/mach-kirkwood/include/mach/entry-macro.S

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 
 * warranty of any kind, whether express or implied.

 */



#include <mach/kirkwood.h>

#include <mach/bridge-regs.h>



	.macro  disable_fiq

	.endm

arch/arm/mach-kirkwood/include/mach/kirkwood.h

+15 −38
Original line number Diff line number Diff line
@@ -43,44 +43,6 @@ 
#define KIRKWOOD_PCIE_MEM_PHYS_BASE	0xe0000000

#define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M



/*

 * MBUS bridge registers.

 */

#define BRIDGE_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x20000)

#define  CPU_CONTROL		(BRIDGE_VIRT_BASE | 0x0104)

#define   CPU_RESET		0x00000002

#define  RSTOUTn_MASK		(BRIDGE_VIRT_BASE | 0x0108)

#define   SOFT_RESET_OUT_EN	0x00000004

#define  SYSTEM_SOFT_RESET	(BRIDGE_VIRT_BASE | 0x010c)

#define   SOFT_RESET		0x00000001

#define  BRIDGE_CAUSE		(BRIDGE_VIRT_BASE | 0x0110)

#define  BRIDGE_MASK		(BRIDGE_VIRT_BASE | 0x0114)

#define   BRIDGE_INT_TIMER0	0x0002

#define   BRIDGE_INT_TIMER1	0x0004

#define   BRIDGE_INT_TIMER1_CLR	(~0x0004)

#define  IRQ_VIRT_BASE		(BRIDGE_VIRT_BASE | 0x0200)

#define   IRQ_CAUSE_LOW_OFF	0x0000

#define   IRQ_MASK_LOW_OFF	0x0004

#define   IRQ_CAUSE_HIGH_OFF	0x0010

#define   IRQ_MASK_HIGH_OFF	0x0014

#define  TIMER_VIRT_BASE	(BRIDGE_VIRT_BASE | 0x0300)

#define  L2_CONFIG_REG		(BRIDGE_VIRT_BASE | 0x0128)

#define   L2_WRITETHROUGH	0x00000010



/*

 * Supported devices and revisions.

 */

#define MV88F6281_DEV_ID	0x6281

#define MV88F6281_REV_Z0	0

#define MV88F6281_REV_A0	2



#define MV88F6192_DEV_ID	0x6192

#define MV88F6192_REV_Z0	0

#define MV88F6192_REV_A0	2



#define MV88F6180_DEV_ID	0x6180

#define MV88F6180_REV_A0	2



/*

 * Register Map

 */
@@ -99,6 +61,8 @@ 
#define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2100)

#define  UART1_VIRT_BASE	(DEV_BUS_VIRT_BASE | 0x2100)



#define BRIDGE_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x20000)



#define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)



#define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
@@ -119,5 +83,18 @@ 


#define SDIO_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x90000)



/*

 * Supported devices and revisions.

 */

#define MV88F6281_DEV_ID	0x6281

#define MV88F6281_REV_Z0	0

#define MV88F6281_REV_A0	2



#define MV88F6192_DEV_ID	0x6192

#define MV88F6192_REV_Z0	0

#define MV88F6192_REV_A0	2



#define MV88F6180_DEV_ID	0x6180

#define MV88F6180_REV_A0	2



#endif