Merge "clk: msm: clock: Only make the RPM request for capping BIMC on msm8996v3" (fdb87603) · Commits · e / devices / android_kernel_xiaomi_markw

drivers/clk/msm/clock-mmss-8996.c

+11 −8

Original line number	Original line	Diff line number	Diff line
	@@ -3491,6 +3491,7 @@ static void msm_mmsscc_8996_v3_fixup(void)
	video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;		video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 533000000;
	}		}

			static int is_v2_gpu, is_v3_gpu;
	static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)		static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)
	{		{
	struct msm_rpm_kvp kvp;		struct msm_rpm_kvp kvp;
	@@ -3500,6 +3501,9 @@ static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)
	uint32_t value;		uint32_t value;
	int ret = 0;		int ret = 0;

			if (!is_v3_gpu)
			return ret;

	old_level = find_vdd_level(clk, clk->rate);		old_level = find_vdd_level(clk, clk->rate);
	if (old_level < 0)		if (old_level < 0)
	return old_level;		return old_level;
	@@ -3522,9 +3526,9 @@ static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)
	ret = msm_rpm_send_message(MSM_RPM_CTX_ACTIVE_SET, RPM_MISC_CLK_TYPE,		ret = msm_rpm_send_message(MSM_RPM_CTX_ACTIVE_SET, RPM_MISC_CLK_TYPE,
	GPU_REQ_ID, &kvp, 1);		GPU_REQ_ID, &kvp, 1);
	if (ret)		if (ret)
	pr_err("%s: Sending the RPM message failed (value - %u)\n",		WARN_ONCE(1, "%s: Sending the RPM message failed (value - %u)\n",
	__func__, value);		__func__, value);
	return ret;		return 0;
	}		}

	static int of_get_fmax_vdd_class(struct platform_device pdev, struct clk c,		static int of_get_fmax_vdd_class(struct platform_device pdev, struct clk c,
	@@ -3584,14 +3588,13 @@ static int of_get_fmax_vdd_class(struct platform_device pdev, struct clk c,
	return 0;		return 0;
	}		}

	static int is_v2_gpu;
	static void print_opp_table(struct device *dev)		static void print_opp_table(struct device *dev)
	{		{
	struct clk *gpu_clk = &gfx3d_clk_src.c;		struct clk *gpu_clk = &gfx3d_clk_src.c;
	struct dev_pm_opp *opp;		struct dev_pm_opp *opp;
	int i;		int i;

	if (is_v2_gpu)		if (is_v2_gpu \|\| is_v3_gpu)
	gpu_clk = &gfx3d_clk_src_v2.c;		gpu_clk = &gfx3d_clk_src_v2.c;

	pr_info("OPP table for GPU core clock:\n");		pr_info("OPP table for GPU core clock:\n");
	@@ -3614,7 +3617,7 @@ static void populate_gpu_opp_table(struct platform_device *pdev)
	int i, ret, uv, corner;		int i, ret, uv, corner;
	unsigned long rate = 0;		unsigned long rate = 0;

	if (is_v2_gpu) {		if (is_v2_gpu \|\| is_v3_gpu) {
	gpu_clk = &gfx3d_clk_src_v2.c;		gpu_clk = &gfx3d_clk_src_v2.c;
	vdd = gpu_clk->vdd_class;		vdd = gpu_clk->vdd_class;
	}		}
	@@ -3888,10 +3891,10 @@ int msm_gpucc_8996_probe(struct platform_device *pdev)
	}		}

	is_v2_gpu = of_device_is_compatible(pdev->dev.of_node,		is_v2_gpu = of_device_is_compatible(pdev->dev.of_node,
	"qcom,gpucc-8996-v2") \|\|		"qcom,gpucc-8996-v2");
	of_device_is_compatible(pdev->dev.of_node,		is_v3_gpu = of_device_is_compatible(pdev->dev.of_node,
	"qcom,gpucc-8996-v3");		"qcom,gpucc-8996-v3");
	if (!is_v2_gpu) {		if (!is_v2_gpu && !is_v3_gpu) {
	rc = of_get_fmax_vdd_class(pdev, &gfx3d_clk_src.c,		rc = of_get_fmax_vdd_class(pdev, &gfx3d_clk_src.c,
	"qcom,gfxfreq-corner-v0");		"qcom,gfxfreq-corner-v0");
	if (rc) {		if (rc) {