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Commit fd59b534 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "dwc3-msm: Enable cfg_ahb_clk before using AHB2PHY register"

parents 84a24c5b 6ff7e3ed

arch/arm/boot/dts/qcom/mdm9640.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -644,10 +644,11 @@ 
			 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb30_sleep_clk>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>;

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;



		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

			      "ref_clk", "xo";

			      "ref_clk", "xo", "cfg_ahb_clk";



		dwc3@8a00000 {

			compatible = "synopsys,dwc3";

arch/arm/boot/dts/qcom/mdmcalifornium.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -563,10 +563,11 @@ 
			 <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,

			 <&clock_gcc clk_gcc_usb30_sleep_clk>,

			 <&clock_gcc clk_ln_bb_clk>,

			 <&clock_gcc clk_cxo_dwc3_clk>;

			 <&clock_gcc clk_cxo_dwc3_clk>,

			 <&clock_gcc clk_gcc_usb_phy_cfg_ahb_clk>;



		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",

			      "ref_clk", "xo";

			      "ref_clk", "xo", "cfg_ahb_clk";



		dwc3@8a00000 {

			compatible = "snps,dwc3";

drivers/usb/dwc3/dwc3-msm.c

+12 −0
Original line number Diff line number Diff line
@@ -166,6 +166,7 @@ struct dwc3_msm { 
	unsigned int		utmi_clk_rate;

	struct clk		*utmi_clk_src;

	struct clk		*bus_aggr_clk;

	struct clk		*cfg_ahb_clk;

	struct regulator	*dwc3_gdsc;



	struct usb_phy		*hs_phy, *ss_phy;
@@ -1205,6 +1206,7 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) 


	/* Configure AHB2PHY for one wait state read/write */

	if (mdwc->ahb2phy_base) {

		clk_prepare_enable(mdwc->cfg_ahb_clk);

		val = readl_relaxed(mdwc->ahb2phy_base +

				PERIPH_SS_AHB2PHY_TOP_CFG);

		if (val != ONE_READ_WRITE_WAIT) {
@@ -1213,6 +1215,7 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) 
			/* complete above write before configuring USB PHY. */

			mb();

		}

		clk_disable_unprepare(mdwc->cfg_ahb_clk);

	}



	dwc3_core_init(dwc);
@@ -2090,6 +2093,13 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) 
	if (IS_ERR(mdwc->bus_aggr_clk))

		mdwc->bus_aggr_clk = NULL;



	mdwc->cfg_ahb_clk = devm_clk_get(mdwc->dev, "cfg_ahb_clk");

	if (IS_ERR(mdwc->cfg_ahb_clk)) {

		dev_err(mdwc->dev, "failed to get cfg_ahb_clk\n");

		ret = PTR_ERR(mdwc->cfg_ahb_clk);

		return ret;

	}



	return 0;

}
@@ -2262,6 +2272,7 @@ static int dwc3_msm_probe(struct platform_device *pdev) 
			dev_err(dev, "couldn't find ahb2phy_base addr.\n");

			mdwc->ahb2phy_base = NULL;

		} else {

			clk_prepare_enable(mdwc->cfg_ahb_clk);

			/* Configure AHB2PHY for one wait state read/write*/

			val = readl_relaxed(mdwc->ahb2phy_base +

					PERIPH_SS_AHB2PHY_TOP_CFG);
@@ -2272,6 +2283,7 @@ static int dwc3_msm_probe(struct platform_device *pdev) 
				/* complete above write before using USB PHY */

				mb();

			}

			clk_disable_unprepare(mdwc->cfg_ahb_clk);

		}

	}