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Commit fd115e68 authored by Mayank Rana's avatar Mayank Rana Committed by Gerrit - the friendly Code Review server
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dwc3: core: Don't perform controller and PHYs soft reset 



Controller and PHY soft reset may result in unknown flip-flop state
resulting in undefined issues. Soft reset is not required as
Controller and PHY are reset using GCC anyway.

Change-Id: I6c2eedd2642ff86b03cf47c97808e461ef5e8f41
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 2f867742

drivers/usb/dwc3/core.c

+0 −57
Original line number Diff line number Diff line
@@ -130,60 +130,6 @@ static int dwc3_init_usb_phys(struct dwc3 *dwc) 
	return 0;

}



/**

 * Peforms core soft reset and PHY soft reset of HS and SS PHYs.

 * If used as a part of POR or init sequence it is recommended

 * that we should perform hard reset and init of the PHYs prior

 * to invoking this function.

 * @dwc: pointer to our context structure

*/

static void dwc3_core_and_phy_soft_reset(struct dwc3 *dwc)

{

	u32		reg;



	/* Before Resetting PHY, put Core in Reset */

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg |= DWC3_GCTL_CORESOFTRESET;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);



	/* Assert USB3 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	usleep_range(1000, 1200);



	/* Clear USB3 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

	reg &= ~DWC3_GUSB3PIPECTL_DELAYP1TRANS;

	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);



	/* Assert USB2 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	usleep_range(1000, 1200);



	/* Clear USB2 PHY reset */

	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;

	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);



	usleep_range(200, 500);



	/* After PHYs are stable we can take Core out of reset state */

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);

	reg &= ~DWC3_GCTL_CORESOFTRESET;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);



	usleep_range(1000, 1200);

}



/**

 * dwc3_core_reset - Issues core soft reset and PHY reset

 * @dwc: pointer to our context structure
@@ -206,9 +152,6 @@ static int dwc3_core_reset(struct dwc3 *dwc) 


	dwc3_notify_event(dwc, DWC3_CONTROLLER_RESET_EVENT);



	/* Perform core and PHY soft reset */

	dwc3_core_and_phy_soft_reset(dwc);



	dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT);



	return 0;