Commit fcde2bf0 authored Oct 19, 2011 by Vladimir Zapolskiy Committed by Greg Kroah-Hartman Oct 19, 2011

staging: tidspbridge: MMU2 registers are limited to 32-bit data access



According to OMAP3 TRM access to MMU registers shall be strictly 32-bit
aligned.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

parent 6b7200fe

drivers/staging/tidspbridge/hw/hw_mmu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -558,5 +558,5 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,

		void hw_mmu_tlb_flush_all(const void __iomem *base)
		{
		__raw_writeb(1, base + MMU_GFLUSH);
		__raw_writel(1, base + MMU_GFLUSH);
		}