Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fcd5c127 authored by Arun KS's avatar Arun KS
Browse files

soc: qcom: pil-q6v5: Modify reset sequence to mitigate in-rush current 



Few chipsets with 1.8.0 version of qdsp6v56 have in rush current issues.
Use the modified reset sequence to further mitigate the in-rush current for
those chipsets.

Add a new device tree property "qcom,qdsp6v56-1-8-inrush-current," to
support this.

Change-Id: I14e63d38923af23f17ed2bbdc302d93852ab3023
Signed-off-by: default avatarArun KS <arunks@codeaurora.org>
parent 8c550138

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ Optional properties: 
- qcom,pil-force-shutdown: Boolean. If set, the SSR framework will not trigger graceful shutdown

                           on behalf of the subsystem driver.

- qcom,qdsp6v56-1-8: Boolean- Present if the qdsp version is v56 1.8

- qcom,qdsp6v56-1-8-inrush-current: Boolean- Present if the qdsp version is V56 1.8 and has in-rush

				    current issue.



Example:

	qcom,mss@fc880000 {

drivers/soc/qcom/pil-q6v5.c

+37 −0
Original line number Diff line number Diff line
@@ -391,6 +391,39 @@ static int __pil_q6v55_reset(struct pil_desc *pil) 
			 */

			udelay(1);

		}

	} else if (drv->qdsp6v56_1_8_inrush_current) {

		/* Deassert QDSP6 compiler memory clamp */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);

		val &= ~QDSP6v55_CLAMP_QMC_MEM;

		writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



		/* Deassert memory peripheral sleep and L2 memory standby */

		val |= (Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N);

		writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);



		/* Turn on L1, L2, ETB and JU memories 1 at a time */

		val = readl_relaxed(drv->reg_base + QDSP6SS_MEM_PWR_CTL);

		for (i = 19; i >= 6; i--) {

			val |= BIT(i);

			writel_relaxed(val, drv->reg_base +

						QDSP6SS_MEM_PWR_CTL);

			/*

			 * Wait for 1us for both memory peripheral and

			 * data array to turn on.

			 */

			udelay(1);

		}



		for (i = 0 ; i <= 5 ; i++) {

			val |= BIT(i);

			writel_relaxed(val, drv->reg_base +

						QDSP6SS_MEM_PWR_CTL);

			/*

			 * Wait for 1us for both memory peripheral and

			 * data array to turn on.

			 */

			udelay(1);

		}

	} else {

		/* Turn on memories. */

		val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL);
@@ -531,6 +564,10 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	drv->qdsp6v56_1_8 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v56-1-8");



	drv->qdsp6v56_1_8_inrush_current = of_property_read_bool(

						pdev->dev.of_node,

						"qcom,qdsp6v56-1-8-inrush-current");



	drv->non_elf_image = of_property_read_bool(pdev->dev.of_node,

						"qcom,mba-image-is-not-elf");

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ struct q6v5_data { 
	bool qdsp6v56_1_3;

	bool qdsp6v56_1_5;

	bool qdsp6v56_1_8;

	bool qdsp6v56_1_8_inrush_current;

	bool non_elf_image;

	bool restart_reg_sec;

	bool override_acc;